Skip to content

Commit 5a7e72d

Browse files
wzssyqawzssyqa
authored
Hexagon: sfmax/sfmin instructions are IEEE754-2019 (llvm#139056)
The min/max instructions of Hexagon follow IEEE754-2019 minimumNumber/maximumNumber, aka FMINIMUMNUM and FMAXIMUMNUM instead of FMAXNUM and FMINNUM
1 parent 691ca55 commit 5a7e72d

File tree

6 files changed

+109
-35
lines changed

6 files changed

+109
-35
lines changed

‎llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

+11-7
Original file line numberDiff line numberDiff line change
@@ -1499,8 +1499,9 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
14991499
// - indexed loads and stores (pre-/post-incremented),
15001500
// - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
15011501
// ConstantFP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
1502-
// FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
1503-
// FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
1502+
// FLOG, FLOG2, FLOG10, FMAXIMUMNUM, FMINIMUMNUM, FNEARBYINT, FRINT, FROUND,
1503+
// TRAP, FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG,
1504+
// ZERO_EXTEND_VECTOR_INREG,
15041505
// which default to "expand" for at least one type.
15051506

15061507
// Misc operations.
@@ -1638,6 +1639,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
16381639

16391640
// Set the action for vector operations to "expand", then override it with
16401641
// either "custom" or "legal" for specific cases.
1642+
// clang-format off
16411643
static const unsigned VectExpOps[] = {
16421644
// Integer arithmetic:
16431645
ISD::ADD, ISD::SUB, ISD::MUL, ISD::SDIV, ISD::UDIV,
@@ -1652,7 +1654,8 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
16521654
ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2,
16531655
ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC,
16541656
ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR,
1655-
ISD::FMINNUM, ISD::FMAXNUM, ISD::FSINCOS, ISD::FLDEXP,
1657+
ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM,
1658+
ISD::FSINCOS, ISD::FLDEXP,
16561659
// Misc:
16571660
ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool,
16581661
// Vector:
@@ -1662,6 +1665,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
16621665
ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE,
16631666
ISD::SPLAT_VECTOR,
16641667
};
1668+
// clang-format on
16651669

16661670
for (MVT VT : MVT::fixedlen_vector_valuetypes()) {
16671671
for (unsigned VectExpOp : VectExpOps)
@@ -1784,8 +1788,8 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
17841788
setOperationAction(ISD::FMUL, MVT::f64, Expand);
17851789
setOperationAction(ISD::FDIV, MVT::f32, Custom);
17861790

1787-
setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
1788-
setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
1791+
setOperationAction(ISD::FMINIMUMNUM, MVT::f32, Legal);
1792+
setOperationAction(ISD::FMAXIMUMNUM, MVT::f32, Legal);
17891793

17901794
setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
17911795
setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
@@ -1833,8 +1837,8 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
18331837
setOperationAction(ISD::FSUB, MVT::f64, Legal);
18341838
}
18351839
if (Subtarget.hasV67Ops()) {
1836-
setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
1837-
setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
1840+
setOperationAction(ISD::FMINIMUMNUM, MVT::f64, Legal);
1841+
setOperationAction(ISD::FMAXIMUMNUM, MVT::f64, Legal);
18381842
setOperationAction(ISD::FMUL, MVT::f64, Legal);
18391843
}
18401844

‎llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp

+6-6
Original file line numberDiff line numberDiff line change
@@ -127,8 +127,8 @@ HexagonTargetLowering::initializeHVXLowering() {
127127
setOperationAction(ISD::FADD, T, Legal);
128128
setOperationAction(ISD::FSUB, T, Legal);
129129
setOperationAction(ISD::FMUL, T, Legal);
130-
setOperationAction(ISD::FMINNUM, T, Legal);
131-
setOperationAction(ISD::FMAXNUM, T, Legal);
130+
setOperationAction(ISD::FMINIMUMNUM, T, Legal);
131+
setOperationAction(ISD::FMAXIMUMNUM, T, Legal);
132132

133133
setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom);
134134
setOperationAction(ISD::EXTRACT_SUBVECTOR, T, Custom);
@@ -164,8 +164,8 @@ HexagonTargetLowering::initializeHVXLowering() {
164164
setOperationAction(ISD::FADD, P, Custom);
165165
setOperationAction(ISD::FSUB, P, Custom);
166166
setOperationAction(ISD::FMUL, P, Custom);
167-
setOperationAction(ISD::FMINNUM, P, Custom);
168-
setOperationAction(ISD::FMAXNUM, P, Custom);
167+
setOperationAction(ISD::FMINIMUMNUM, P, Custom);
168+
setOperationAction(ISD::FMAXIMUMNUM, P, Custom);
169169
setOperationAction(ISD::SETCC, P, Custom);
170170
setOperationAction(ISD::VSELECT, P, Custom);
171171

@@ -3172,8 +3172,8 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const {
31723172
case ISD::FADD:
31733173
case ISD::FSUB:
31743174
case ISD::FMUL:
3175-
case ISD::FMINNUM:
3176-
case ISD::FMAXNUM:
3175+
case ISD::FMINIMUMNUM:
3176+
case ISD::FMAXIMUMNUM:
31773177
case ISD::MULHS:
31783178
case ISD::MULHU:
31793179
case ISD::AND:

‎llvm/lib/Target/Hexagon/HexagonPatterns.td

+4-4
Original file line numberDiff line numberDiff line change
@@ -1579,8 +1579,8 @@ def: OpR_RR_pat<C2_and, Mul, v8i1, V8I1>;
15791579
def: OpR_RR_pat<F2_sfadd, pf2<fadd>, f32, F32>;
15801580
def: OpR_RR_pat<F2_sfsub, pf2<fsub>, f32, F32>;
15811581
def: OpR_RR_pat<F2_sfmpy, pf2<fmul>, f32, F32>;
1582-
def: OpR_RR_pat<F2_sfmin, pf2<fminnum>, f32, F32>;
1583-
def: OpR_RR_pat<F2_sfmax, pf2<fmaxnum>, f32, F32>;
1582+
def: OpR_RR_pat<F2_sfmin, pf2<fminimumnum>, f32, F32>;
1583+
def: OpR_RR_pat<F2_sfmax, pf2<fmaximumnum>, f32, F32>;
15841584

15851585
let Predicates = [HasV66] in {
15861586
def: OpR_RR_pat<F2_dfadd, pf2<fadd>, f64, F64>;
@@ -1600,8 +1600,8 @@ let Predicates = [HasV67,UseUnsafeMath], AddedComplexity = 50 in {
16001600
def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy $Rs, $Rt)>;
16011601
}
16021602
let Predicates = [HasV67] in {
1603-
def: OpR_RR_pat<F2_dfmin, pf2<fminnum>, f64, F64>;
1604-
def: OpR_RR_pat<F2_dfmax, pf2<fmaxnum>, f64, F64>;
1603+
def: OpR_RR_pat<F2_dfmin, pf2<fminimumnum>, f64, F64>;
1604+
def: OpR_RR_pat<F2_dfmax, pf2<fmaximumnum>, f64, F64>;
16051605

16061606
def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy (F2_dfmpyfix $Rs, $Rt),
16071607
(F2_dfmpyfix $Rt, $Rs))>;

‎llvm/lib/Target/Hexagon/HexagonPatternsHVX.td

+8-8
Original file line numberDiff line numberDiff line change
@@ -508,10 +508,10 @@ let Predicates = [UseHVXV68, UseHVX128B, UseHVXQFloat] in {
508508
defm: MinMax_pats<V6_vmin_sf, V6_vmax_sf, vselect, setgt, VecQ32, HVF32>;
509509
defm: MinMax_pats<V6_vmin_sf, V6_vmax_sf, vselect, setogt, VecQ32, HVF32>;
510510
}
511-
def: OpR_RR_pat<V6_vmin_hf, pf2<fminnum>, VecF16, HVF16>;
512-
def: OpR_RR_pat<V6_vmax_hf, pf2<fmaxnum>, VecF16, HVF16>;
513-
def: OpR_RR_pat<V6_vmin_sf, pf2<fminnum>, VecF32, HVF32>;
514-
def: OpR_RR_pat<V6_vmax_sf, pf2<fmaxnum>, VecF32, HVF32>;
511+
def: OpR_RR_pat<V6_vmin_hf, pf2<fminimumnum>, VecF16, HVF16>;
512+
def: OpR_RR_pat<V6_vmax_hf, pf2<fmaximumnum>, VecF16, HVF16>;
513+
def: OpR_RR_pat<V6_vmin_sf, pf2<fminimumnum>, VecF32, HVF32>;
514+
def: OpR_RR_pat<V6_vmax_sf, pf2<fmaximumnum>, VecF32, HVF32>;
515515
}
516516

517517
let Predicates = [UseHVXV68, UseHVX128B, UseHVXIEEEFP] in {
@@ -521,10 +521,10 @@ let Predicates = [UseHVXV68, UseHVX128B, UseHVXIEEEFP] in {
521521
defm: MinMax_pats<V6_vfmin_sf, V6_vfmax_sf, vselect, setgt, VecQ32, HVF32>;
522522
defm: MinMax_pats<V6_vfmin_sf, V6_vfmax_sf, vselect, setogt, VecQ32, HVF32>;
523523
}
524-
def: OpR_RR_pat<V6_vfmin_hf, pf2<fminnum>, VecF16, HVF16>;
525-
def: OpR_RR_pat<V6_vfmax_hf, pf2<fmaxnum>, VecF16, HVF16>;
526-
def: OpR_RR_pat<V6_vfmin_sf, pf2<fminnum>, VecF32, HVF32>;
527-
def: OpR_RR_pat<V6_vfmax_sf, pf2<fmaxnum>, VecF32, HVF32>;
524+
def: OpR_RR_pat<V6_vfmin_hf, pf2<fminimumnum>, VecF16, HVF16>;
525+
def: OpR_RR_pat<V6_vfmax_hf, pf2<fmaximumnum>, VecF16, HVF16>;
526+
def: OpR_RR_pat<V6_vfmin_sf, pf2<fminimumnum>, VecF32, HVF32>;
527+
def: OpR_RR_pat<V6_vfmax_sf, pf2<fmaximumnum>, VecF32, HVF32>;
528528
}
529529

530530
let Predicates = [UseHVX] in {

‎llvm/test/CodeGen/Hexagon/fminmax-v67.ll

+41-4
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,7 @@
22

33

44
; CHECK-LABEL: t1
5-
; CHECK: dfmax
5+
; CHECK: call fmax
66

77
define dso_local double @t1(double %a, double %b) local_unnamed_addr {
88
entry:
@@ -11,7 +11,7 @@ entry:
1111
}
1212

1313
; CHECK-LABEL: t2
14-
; CHECK: dfmin
14+
; CHECK: call fmin
1515

1616
define dso_local double @t2(double %a, double %b) local_unnamed_addr {
1717
entry:
@@ -20,7 +20,7 @@ entry:
2020
}
2121

2222
; CHECK-LABEL: t3
23-
; CHECK: sfmax
23+
; CHECK: call fmaxf
2424

2525
define dso_local float @t3(float %a, float %b) local_unnamed_addr {
2626
entry:
@@ -29,14 +29,51 @@ entry:
2929
}
3030

3131
; CHECK-LABEL: t4
32-
; CHECK: sfmin
32+
; CHECK: call fminf
3333

3434
define dso_local float @t4(float %a, float %b) local_unnamed_addr {
3535
entry:
3636
%0 = tail call float @llvm.minnum.f32(float %a, float %b)
3737
ret float %0
3838
}
3939

40+
; CHECK-LABEL: t1num
41+
; CHECK: dfmax
42+
43+
define dso_local double @t1num(double %a, double %b) local_unnamed_addr {
44+
entry:
45+
%0 = tail call double @llvm.maximumnum.f64(double %a, double %b)
46+
ret double %0
47+
}
48+
49+
; CHECK-LABEL: t2num
50+
; CHECK: dfmin
51+
52+
define dso_local double @t2num(double %a, double %b) local_unnamed_addr {
53+
entry:
54+
%0 = tail call double @llvm.minimumnum.f64(double %a, double %b)
55+
ret double %0
56+
}
57+
58+
; CHECK-LABEL: t3num
59+
; CHECK: sfmax
60+
61+
define dso_local float @t3num(float %a, float %b) local_unnamed_addr {
62+
entry:
63+
%0 = tail call float @llvm.maximumnum.f32(float %a, float %b)
64+
ret float %0
65+
}
66+
67+
; CHECK-LABEL: t4num
68+
; CHECK: sfmin
69+
70+
define dso_local float @t4num(float %a, float %b) local_unnamed_addr {
71+
entry:
72+
%0 = tail call float @llvm.minimumnum.f32(float %a, float %b)
73+
ret float %0
74+
}
75+
76+
4077
declare double @llvm.minnum.f64(double, double) #1
4178
declare double @llvm.maxnum.f64(double, double) #1
4279
declare float @llvm.maxnum.f32(float, float) #1

‎llvm/test/CodeGen/Hexagon/fminmax.ll

+39-6
Original file line numberDiff line numberDiff line change
@@ -3,22 +3,55 @@
33
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
44
target triple = "hexagon"
55

6-
; CHECK-LABEL: minimum
7-
; CHECK: sfmin
8-
define float @minimum(float %x, float %y) #0 {
6+
; CHECK-LABEL: cfminf
7+
; CHECK: call fminf
8+
define float @cfminf(float %x, float %y) #0 {
99
entry:
1010
%call = tail call float @fminf(float %x, float %y) #1
1111
ret float %call
1212
}
1313

14-
; CHECK-LABEL: maximum
15-
; CHECK: sfmax
16-
define float @maximum(float %x, float %y) #0 {
14+
; CHECK-LABEL: cfmaxf
15+
; CHECK: call fmaxf
16+
define float @cfmaxf(float %x, float %y) #0 {
1717
entry:
1818
%call = tail call float @fmaxf(float %x, float %y) #1
1919
ret float %call
2020
}
2121

22+
; CHECK-LABEL: minnum
23+
; CHECK: call fminf
24+
define float @minnum(float %x, float %y) #0 {
25+
entry:
26+
%call = tail call float @llvm.minnum.f32(float %x, float %y) #1
27+
ret float %call
28+
}
29+
30+
; CHECK-LABEL: maxnum
31+
; CHECK: call fmaxf
32+
define float @maxnum(float %x, float %y) #0 {
33+
entry:
34+
%call = tail call float @llvm.maxnum.f32(float %x, float %y) #1
35+
ret float %call
36+
}
37+
38+
; CHECK-LABEL: minimumnum
39+
; CHECK: sfmin
40+
define float @minimumnum(float %x, float %y) #0 {
41+
entry:
42+
%call = tail call float @llvm.minimumnum.f32(float %x, float %y) #1
43+
ret float %call
44+
}
45+
46+
; CHECK-LABEL: maximumnum
47+
; CHECK: sfmax
48+
define float @maximumnum(float %x, float %y) #0 {
49+
entry:
50+
%call = tail call float @llvm.maximumnum.f32(float %x, float %y) #1
51+
ret float %call
52+
}
53+
54+
2255
declare float @fminf(float, float) #0
2356
declare float @fmaxf(float, float) #0
2457

0 commit comments

Comments
 (0)