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ustcpetergu: Added COD code
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‎计算机组成原理/codes/ustcpetergu/README.md

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### 2020 年春季学期 COD 实验报告 & 代码
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原项目/历史记录请见 https://github.com/ustcpetergu/USTC-COD-Labs/
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- Lab1: ALU & sort
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- Lab2: Regfile & RAM & FIFO
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- Lab3: Single cycle CPU
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- Lab4: Multiple cycle CPU
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- Lab5: 5-stage pipeline CPU
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- Lab6: CPU & UART on ebaz4205 (testing video in report.md)
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Rebuild projects from TCL(for example):
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```
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vivado -mode batch -source lab6.tcl -tclargs --project_name lab6
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```

‎计算机组成原理/codes/ustcpetergu/ip/alu/component.xml

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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:name>WIDTH</spirit:name>
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‎计算机组成原理/codes/ustcpetergu/ip/alu/src/alu.v

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`timescale 1ns / 1ps
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// ALU
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// 2020 COD Lab1
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// ustcpetergu
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module alu
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#(parameter WIDTH = 32)
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(
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input [2:0]m, // selection
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input [WIDTH-1:0]a, b, // input
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output [WIDTH-1:0]y, // result
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output zf, // zero flag
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output cf, // carry out flag: WIDTH bit
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output of // overflow flag: WIDTH-1 sign bit
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);
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reg [WIDTH-1:0]regy;
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reg regcf;
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reg regof;
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reg regzf;
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assign y = regy;
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assign cf = regcf;
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assign of = regof;
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assign zf = regzf;
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// assign zf = (regy == 0);
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always @ (a, b, m) begin
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case(m)
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3'b000: begin // add
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{regcf, regy} = a + b;
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regof = (!a[WIDTH-1] & !b[WIDTH-1] & regy[WIDTH-1]) |
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(a[WIDTH-1] & b[WIDTH-1] & !regy[WIDTH-1]);
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regzf = (regy == 0);
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end
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3'b001: begin // sub
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{regcf, regy} = a - b;
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regof = (!a[WIDTH-1] & b[WIDTH-1] & regy[WIDTH-1]) |
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(a[WIDTH-1] & !b[WIDTH-1] & !regy[WIDTH-1]);
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regzf = (regy == 0);
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end
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3'b010: begin // and
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regy = a & b;
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regzf = (regy == 0);
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regcf = 0;
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regof = 0;
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end
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3'b011: begin // or
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regy = a | b;
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regzf = (regy == 0);
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regcf = 0;
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regof = 0;
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end
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3'b100: begin // xor
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regy = a ^ b;
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regzf = (regy == 0);
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regcf = 0;
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regof = 0;
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end
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default: begin // error
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regy = 0;
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regzf = 0;
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regcf = 0;
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regof = 0;
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end
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endcase
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end
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endmodule

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