@@ -31,6 +31,24 @@ PRIVATE_NAMESPACE_BEGIN
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using RTLIL::id2cstr;
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+ struct CleanerPool : SigPool
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+ {
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+ bool check_all_def (const RTLIL::SigSpec &sig) const
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+ {
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+ for (auto &bit : sig) {
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+ if (bit.wire != NULL && bits.count (bit) == 0 )
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+ return false ;
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+ if (bit.wire == NULL && bit.data == RTLIL::State::Sx)
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+ return false ;
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+ }
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+ return true ;
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+ }
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+ bool check_def (const RTLIL::SigBit &bit) const
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+ {
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+ return (bit.wire != NULL && bits.count (bit)) || (bit.wire == NULL && bit.data != RTLIL::State::Sx);
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+ }
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+ };
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+
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struct keep_cache_t
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{
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Design *design;
@@ -356,7 +374,7 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
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// used signals pre-sigmapped
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SigPool raw_used_signals;
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// used signals sigmapped, ignoring drivers (we keep track of this to set `unused_bits`)
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- SigPool used_signals_nodrivers;
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+ CleanerPool used_signals_nodrivers;
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// gather the usage information for cells
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for (auto &it : module->cells_ ) {
@@ -472,14 +490,14 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
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module->connect (new_conn);
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}
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- if (!used_signals_nodrivers.check_all (s2)) {
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+ if (!used_signals_nodrivers.check_all_def (s2)) {
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std::string unused_bits;
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for (int i = 0 ; i < GetSize (s2); i++) {
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- if (s2[i].wire == NULL )
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- continue ;
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- if (!used_signals_nodrivers.check (s2[i])) {
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+ if (( s2[i].wire == NULL ) && (s2[i]. data != RTLIL::State::Sx) )
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+ continue ;
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+ if (!used_signals_nodrivers.check_def (s2[i])) {
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if (!unused_bits.empty ())
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- unused_bits += " " ;
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+ unused_bits += " " ;
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unused_bits += stringf (" %d" , i);
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}
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}
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