Generated Verilog should be more readable

[nmigen-issue-migration]

Issue by whitequark
Tuesday Jun 11, 2019 at 04:09 GMT
Originally opened as m-labs/nmigen#98

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This is solely blocked on Yosys issue YosysHQ/yosys#726. It's in my queue for some time, but the threshold for merging it is fairly high (multiple days of randomized testing), so I haven't been able to push it to completion yet.

[nmigen-issue-migration]

Comment by mithro
Tuesday Jun 11, 2019 at 07:48 GMT

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@whitequark Would having access to a bunch of CPU resources help with the randomized testing?

[nmigen-issue-migration]

Comment by whitequark
Tuesday Jun 11, 2019 at 07:51 GMT

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@mithro It's kind of a pain to set up VlogHammer in the first place. I think I can use the M-Labs machine for testing that once I have a general confidence in the correctness of the changes to that pass.

[nmigen-issue-migration]

Comment by whitequark
Sunday Jul 14, 2019 at 03:34 GMT

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Would having access to a bunch of CPU resources help with the randomized testing?

Actually, what kind of resources can you provide? If it's something monstrous like a 64-core machine I'd be interested. VlogHammer is embarrassingly parallel, so it pays off to use a huge number of slower cores.

[nmigen-issue-migration]

Comment by mithro
Monday Jul 15, 2019 at 14:01 GMT

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I could provide pretty much anything on the list at https://cloud.google.com/compute/docs/machine-types

Anything like the following might work?

• n1-standard-96
• n1-highmem-64
• n1-highcpu-96

[nmigen-issue-migration]

Comment by whitequark
Wednesday Jul 31, 2019 at 04:58 GMT

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Fixing YosysHQ/yosys#726 proved to be extraordinarily complex, so bumping this from 0.1 milestone.