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Issues list

Document FIFO properties improvement
#1538 opened Oct 28, 2024 by rroohhh
1
Formatting of enums without shape in a data.StructLayout does not work improvement
#1534 opened Oct 14, 2024 by rroohhh
3
Improve the names given to anonymous submodules improvement
#1525 opened Oct 4, 2024 by whitequark
Clarify documentation on the module usage in wiring.connect() improvement
#1509 opened Sep 10, 2024 by 5aji
1
Document release process improvement
#1502 opened Sep 5, 2024 by whitequark
2
Usability: better documentation required for Instance instantiation/interaction with platform resources improvement
#1470 opened Aug 2, 2024 by psychogenic 0.6
Improve diagnostics on module.domain/module.domains mixup improvement
#1431 opened Jun 28, 2024 by mcclure
1
Warn after simulation ends if a domain's clock isn't driven by either logic or testbench improvement
#1415 opened Jun 20, 2024 by whitequark 0.6
AttributeError caused by UnusedElaboratable after an elaboratable has failed its initialization improvement
#1382 opened Jun 14, 2024 by jfng
1
Kill Value._lhs_signals and Value._rhs_signals improvement meta:help-wanted
#1222 opened Mar 21, 2024 by whitequark
Normalize diagnostics to use either a backtick or a single quote, not both at random improvement meta:help-wanted
#1160 opened Feb 27, 2024 by whitequark
2
Structured source locations improvement meta:help-wanted
#1131 opened Feb 13, 2024 by whitequark 0.6
Add an amaranth.hdl._ast.Match node, use it for Value.matches, and delegate from Case() to Value.matches improvement meta:help-wanted
#1074 opened Jan 31, 2024 by whitequark
iCE40 BRAM errata workaround silently disappears once a clock domain named "sync" is defined improvement
#943 opened Oct 24, 2023 by cbiffle
3
Code duplication when using a Value multiple times improvement
#787 opened May 22, 2023 by tilk
2
Document the Python APIs in amaranth.hdl improvement
#785 opened May 15, 2023 by whitequark
1 task done
0.6
Can I add typehints? improvement
#725 opened Oct 30, 2022 by RobertBaruch
9
Simulation : abort simulation when step() does not converge improvement meta:help-wanted simulator:pysim
#703 opened Apr 21, 2022 by sporniket
4
Guidance on naming - when to say "Amaranth HDL" versus just "Amaranth". improvement
#660 opened Dec 13, 2021 by martinling
7
Determine frequency of Cyclone V clock improvement platform:intel
#655 opened Dec 13, 2021 by Lunaphied
3
Way to start register with "random" value? improvement
#562 opened Dec 14, 2020 by RobertBaruch
15
Simulator with non-passive sync process and no clock added runs indefinitely without emitting a warning improvement simulator:pysim
#442 opened Jul 21, 2020 by the6p4c
2
Emit a warning when an Assign expression is not added to a domain improvement
#423 opened Jul 6, 2020 by kbeckmann
4
Better diagnostics for undefined domain usage improvement
#389 opened May 22, 2020 by matthuszagh
1
Multi-clock formal for AsyncFIFO test cases improvement
#387 opened May 16, 2020 by awygle
ProTip! Exclude everything labeled bug with -label:bug.