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kentlibekentlibe
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mfd: add driver for max42500
The MAX42500 is a multiple function device for power-system monitoring, timestamp recordings and watchdog controls all-together in one SoC package. These features can be used independently or at the same time in a wide range of applications. Signed-off-by: Kent Libetario <Kent.Libetario@analog.com>
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‎drivers/mfd/Kconfig

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@@ -808,6 +808,19 @@ config MFD_MAX14577
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additional drivers must be enabled in order to use the functionality
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of the device.
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config MFD_MAX42500
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bool "Analog Devices MAX42500 Industrial Power System Monitor"
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depends on I2C
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select MFD_CORE
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select REGMAP_I2C
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help
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Say yes here to add support for MAX42500 SoC power-system monitor
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with up to seven voltage monitor. The driver also contains a
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programmable challenge/response watchdog, which is accessible through
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the I2C interface, along with a configurable RESET output. Additional
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drivers can be enabled in order to use the following functionalities
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of the device: GPIO.
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config MFD_MAX77541
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tristate "Analog Devices MAX77541/77540 PMIC Support"
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depends on I2C=y

‎drivers/mfd/Makefile

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@@ -157,6 +157,7 @@ obj-$(CONFIG_MFD_DA9063) += da9063.o
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obj-$(CONFIG_MFD_DA9150) += da9150-core.o
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obj-$(CONFIG_MFD_MAX14577) += max14577.o
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obj-$(CONFIG_MFD_MAX42500) += max42500.o
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obj-$(CONFIG_MFD_MAX77541) += max77541.o
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obj-$(CONFIG_MFD_MAX77620) += max77620.o
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obj-$(CONFIG_MFD_MAX77650) += max77650.o

‎drivers/mfd/max42500.c

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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* MAX42500 - MFD Power System Monitor
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*
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* Copyright 2025 Analog Devices Inc.
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*/
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/max42500.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/regmap.h>
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static const struct mfd_cell max42500_subdev[] = {
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MFD_CELL_NAME("max42500-hwmon"),
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MFD_CELL_NAME("max42500-wdt"),
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};
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static const struct regmap_config max42500_regmap_config = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = MAX42500_REG_CID,
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};
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static int max42500_probe(struct i2c_client *i2c)
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{
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struct regmap *map;
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int ret;
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map = devm_regmap_init_i2c(i2c, &max42500_regmap_config);
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if (IS_ERR(map))
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return PTR_ERR(map);
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ret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO,
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max42500_subdev, ARRAY_SIZE(max42500_subdev),
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NULL, 0, NULL);
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return ret;
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}
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static const struct of_device_id max42500_of_match[] = {
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{ .compatible = "adi,max42500" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, max42500_of_match);
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static struct i2c_driver max42500_driver = {
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.driver = {
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.name = "max42500",
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.of_match_table = max42500_of_match,
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},
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.probe = max42500_probe,
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};
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module_i2c_driver(max42500_driver);
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MODULE_AUTHOR("Kent Libetario <kent.libetario@analog.com>");
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MODULE_DESCRIPTION("MFD driver for MAX42500");
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MODULE_LICENSE("GPL");

‎include/linux/mfd/max42500.h

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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* MAX42500 - Industrial Power System Monitor
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*
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* Copyright 2025 Analog Devices Inc.
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*/
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#ifndef __MFD_MAX42500_H
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#define __MFD_MAX42500_H
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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/* Command registers */
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#define MAX42500_REG_ID 0x00
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#define MAX42500_REG_CONFIG1 0x01
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#define MAX42500_REG_CONFIG2 0x02
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#define MAX42500_REG_VMON 0x03
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#define MAX42500_REG_RSTMAP 0x04
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#define MAX42500_REG_STATOV 0x05
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#define MAX42500_REG_STATUV 0x06
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#define MAX42500_REG_STATOFF 0x07
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#define MAX42500_REG_VIN1 0x08
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#define MAX42500_REG_VIN2 0x09
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#define MAX42500_REG_VIN3 0x0A
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#define MAX42500_REG_VIN4 0x0B
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#define MAX42500_REG_VIN5 0x0C
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#define MAX42500_REG_VINO6 0x0D
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#define MAX42500_REG_VINU6 0x0E
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#define MAX42500_REG_VINO7 0x0F
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#define MAX42500_REG_VINU7 0x10
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#define MAX42500_REG_OVUV1 0x11
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#define MAX42500_REG_OVUV2 0x12
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#define MAX42500_REG_OVUV3 0x13
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#define MAX42500_REG_OVUV4 0x14
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#define MAX42500_REG_OVUV5 0x15
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#define MAX42500_REG_FPSTAT1 0x16
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#define MAX42500_REG_FPSCFG1 0x17
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#define MAX42500_REG_UTIME1 0x18
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#define MAX42500_REG_UTIME2 0x19
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#define MAX42500_REG_UTIME3 0x1A
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#define MAX42500_REG_UTIME4 0x1B
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#define MAX42500_REG_UTIME5 0x1C
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#define MAX42500_REG_UTIME6 0x1D
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#define MAX42500_REG_UTIME7 0x1E
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#define MAX42500_REG_DTIME1 0x1F
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#define MAX42500_REG_DTIME2 0x20
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#define MAX42500_REG_DTIME3 0x21
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#define MAX42500_REG_DTIME4 0x22
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#define MAX42500_REG_DTIME5 0x23
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#define MAX42500_REG_DTIME6 0x24
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#define MAX42500_REG_DTIME7 0x25
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#define MAX42500_REG_WDSTAT 0x26
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#define MAX42500_REG_WDCDIV 0x27
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#define MAX42500_REG_WDCFG1 0x28
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#define MAX42500_REG_WDCFG2 0x29
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#define MAX42500_REG_WDKEY 0x2A
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#define MAX42500_REG_WDLOCK 0x2B
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#define MAX42500_REG_RSTCTRL 0x2C
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#define MAX42500_REG_CID 0x2D
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/* Status error */
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#define MAX42500_STS_ERROR 0xFF
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/* Device chip registers */
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#define MAX42500_CHIP_ID_MASK GENMASK(7, 0)
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#define MAX42500_CHIP_ID(x) FIELD_GET(MAX42500_CHIP_ID_MASK, x)
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#define MAX42500_CHIP_CID_MASK GENMASK(7, 0)
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#define MAX42500_CHIP_CID(x) FIELD_GET(MAX42500_CHIP_CID_MASK, x)
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#define MAX42500_CHIP_CFG2_MASK GENMASK(7, 0)
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#define MAX42500_CHIP_CFG2(x) FIELD_GET(MAX42500_CHIP_PECE_MASK, x)
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#define MAX42500_CHIP_PECE_MASK BIT(0)
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#define MAX42500_CHIP_PECE(x) FIELD_GET(MAX42500_CHIP_PECE_MASK, x)
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#define MAX42500_CHIP_MBST_MASK BIT(1)
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#define MAX42500_CHIP_MBST(x) FIELD_GET(MAX42500_CHIP_MBST_MASK, x)
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#define MAX42500_CHIP_RR_MASK BIT(2)
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#define MAX42500_CHIP_RR(x) FIELD_GET(MAX42500_CHIP_RR_MASK, x)
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/* Voltage Monitor registers */
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#define MAX42500_VMON_VM1_MASK BIT(0)
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#define MAX42500_VMON_VM1(x) FIELD_GET(MAX42500_VMON_VM1_MASK, x)
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#define MAX42500_VMON_VM2_MASK BIT(1)
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#define MAX42500_VMON_VM2(x) FIELD_GET(MAX42500_VMON_VM2_MASK, x)
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#define MAX42500_VMON_VM3_MASK BIT(2)
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#define MAX42500_VMON_VM3(x) FIELD_GET(MAX42500_VMON_VM3_MASK, x)
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#define MAX42500_VMON_VM4_MASK BIT(3)
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#define MAX42500_VMON_VM4(x) FIELD_GET(MAX42500_VMON_VM4_MASK, x)
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#define MAX42500_VMON_VM5_MASK BIT(4)
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#define MAX42500_VMON_VM5(x) FIELD_GET(MAX42500_VMON_VM5_MASK, x)
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#define MAX42500_VMON_VM6_MASK BIT(5)
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#define MAX42500_VMON_VM6(x) FIELD_GET(MAX42500_VMON_VM6_MASK, x)
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#define MAX42500_VMON_VM7_MASK BIT(6)
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#define MAX42500_VMON_VM7(x) FIELD_GET(MAX42500_VMON_VM7_MASK, x)
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#define MAX42500_VMON_VMPD_MASK BIT(7)
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#define MAX42500_VMON_VMPD(x) FIELD_GET(MAX42500_VMON_VMPD_MASK, x)
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#define MAX42500_VMON_RST1_MASK BIT(0)
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#define MAX42500_VMON_RST1(x) FIELD_GET(MAX42500_VMON_RST1_MASK, x)
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#define MAX42500_VMON_RST2_MASK BIT(1)
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#define MAX42500_VMON_RST2(x) FIELD_GET(MAX42500_VMON_RST2_MASK, x)
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#define MAX42500_VMON_RST3_MASK BIT(2)
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#define MAX42500_VMON_RST3(x) FIELD_GET(MAX42500_VMON_RST3_MASK, x)
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#define MAX42500_VMON_RST4_MASK BIT(3)
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#define MAX42500_VMON_RST4(x) FIELD_GET(MAX42500_VMON_RST4_MASK, x)
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#define MAX42500_VMON_RST5_MASK BIT(4)
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#define MAX42500_VMON_RST5(x) FIELD_GET(MAX42500_VMON_RST5_MASK, x)
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#define MAX42500_VMON_RST6_MASK BIT(5)
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#define MAX42500_VMON_RST6(x) FIELD_GET(MAX42500_VMON_RST6_MASK, x)
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#define MAX42500_VMON_RST7_MASK BIT(6)
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#define MAX42500_VMON_RST7(x) FIELD_GET(MAX42500_VMON_RST7_MASK, x)
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#define MAX42500_VMON_PARM_MASK BIT(7)
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#define MAX42500_VMON_PARM(x) FIELD_GET(MAX42500_VMON_PARM_MASK, x)
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#define MAX42500_VMON_1VIN5_MASK GENMASK(7, 0)
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#define MAX42500_VMON_1VIN5(x) FIELD_GET(MAX42500_VMON_1VIN5_MASK, x)
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#define MAX42500_VMON_1VINU5_MASK GENMASK(3, 0)
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#define MAX42500_VMON_1VINU5(x) FIELD_GET(MAX42500_VMON_1VINU5_MASK, x)
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#define MAX42500_VMON_6VINU7_MASK GENMASK(7, 0)
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#define MAX42500_VMON_6VINU7(x) FIELD_GET(MAX42500_VMON_6VINU7_MASK, x)
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#define MAX42500_VMON_1VINO5_MASK GENMASK(7, 4)
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#define MAX42500_VMON_1VINO5(x) FIELD_GET(MAX42500_VMON_1VINO5_MASK, x)
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#define MAX42500_VMON_6VINO7_MASK GENMASK(7, 0)
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#define MAX42500_VMON_6VINO7(x) FIELD_GET(MAX42500_VMON_6VINO7_MASK, x)
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#define MAX42500_VMON_STATOFF_MASK GENMASK(7, 0)
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#define MAX42500_VMON_STATOFF(x) FIELD_GET(MAX42500_VMON_STATOFF_MASK, x)
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#define MAX42500_VMON_STATUV_MASK GENMASK(7, 0)
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#define MAX42500_VMON_STATUV(x) FIELD_GET(MAX42500_VMON_STATUV_MASK, x)
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#define MAX42500_VMON_STATOV_MASK GENMASK(7, 0)
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#define MAX42500_VMON_STATOV(x) FIELD_GET(MAX42500_VMON_STATOV_MASK, x)
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/* Sequence recorder registers */
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#define MAX42500_FPSR_FPSTAT1_MASK GENMASK(7, 0)
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#define MAX42500_FPSR_FPSTAT1(x) FIELD_GET(MAX42500_FPSR_FPSTAT1_MASK, x)
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#define MAX42500_FPSR_FDIV_MASK GENMASK(2, 0)
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#define MAX42500_FPSR_FDIV(x) FIELD_GET(MAX42500_FPSR_FDIV_MASK, x)
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#define MAX42500_FPSR_FPSEN1_MASK BIT(3)
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#define MAX42500_FPSR_FPSEN1(x) FIELD_GET(MAX42500_FPSR_FPSEN1_MASK, x)
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#define MAX42500_FPSR_DVALM_MASK BIT(4)
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#define MAX42500_FPSR_DVALM(x) FIELD_GET(MAX42500_FPSR_DVALM_MASK, x)
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#define MAX42500_FPSR_UVALM_MASK BIT(5)
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#define MAX42500_FPSR_UVALM(x) FIELD_GET(MAX42500_FPSR_UVALM_MASK, x)
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#define MAX42500_FPSR_DVAL_MASK BIT(6)
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#define MAX42500_FPSR_DVAL(x) FIELD_GET(MAX42500_FPSR_DVAL_MASK, x)
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#define MAX42500_FPSR_UVAL_MASK BIT(7)
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#define MAX42500_FPSR_UVAL(x) FIELD_GET(MAX42500_FPSR_UVAL_MASK, x)
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#define MAX42500_FPSR_1UTIM7_MASK GENMASK(7, 0)
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#define MAX42500_FPSR_1UTIM7(x) FIELD_GET(MAX42500_FPSR_1UTIM7_MASK, x)
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#define MAX42500_FPSR_1DTIM7_MASK GENMASK(7, 0)
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#define MAX42500_FPSR_1DTIM7(x) FIELD_GET(MAX42500_FPSR_1DTIM7_MASK, x)
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/* Windowed watchdog register*/
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#define MAX42500_WDOG_WDSTAT_MASK GENMASK(7, 0)
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#define MAX42500_WDOG_WDSTAT(x) FIELD_GET(MAX42500_WDOG_WDSTAT_MASK, x)
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#define MAX42500_WDOG_WDIV_MASK GENMASK(5, 0)
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#define MAX42500_WDOG_WDIV(x) FIELD_GET(MAX42500_WDOG_WDIV_MASK, x)
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#define MAX42500_WDOG_SWW_MASK BIT(6)
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#define MAX42500_WDOG_SWW(x) FIELD_GET(MAX42500_WDOG_SWW_MASK, x)
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#define MAX42500_WDOG_WDOPEN_MASK GENMASK(3, 0)
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#define MAX42500_WDOG_WDOPEN(x) FIELD_GET(MAX42500_WDOG_WDOPEN_MASK, x)
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#define MAX42500_WDOG_WDCLOSE_MASK GENMASK(7, 4)
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#define MAX42500_WDOG_WDCLOSE(x) FIELD_GET(MAX42500_WDOG_WDCLOSE_MASK, x)
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#define MAX42500_WDOG_1UD_MASK GENMASK(2, 0)
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#define MAX42500_WDOG_1UD(x) FIELD_GET(MAX42500_WDOG_1UD_MASK, x)
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#define MAX42500_WDOG_WDEN_MASK BIT(3)
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#define MAX42500_WDOG_WDEN(x) FIELD_GET(MAX42500_WDOG_WDEN_MASK, x)
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#define MAX42500_WDOG_WDKEY_MASK GENMASK(7, 0)
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#define MAX42500_WDOG_WDKEY(x) FIELD_GET(MAX42500_WDOG_WDKEY_MASK, x)
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#define MAX42500_WDOG_WDLOCK_MASK BIT(0)
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#define MAX42500_WDOG_WDLOCK(x) FIELD_GET(MAX42500_WDOG_WDLOCK_MASK, x)
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#define MAX42500_WDOG_RHLD_MASK GENMASK(1, 0)
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#define MAX42500_WDOG_RHLD(x) FIELD_GET(MAX42500_WDOG_RHLD_MASK, x)
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#define MAX42500_WDOG_MR1_MASK BIT(2)
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#define MAX42500_WDOG_MR1(x) FIELD_GET(MAX42500_WDOG_MR1_MASK, x)
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#endif /* __MFD_MAX42500_H */

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