Microcode constant support for Clojure

Cleaned up Ruby constants, too. The whole CONSTANT_N thing makes no sense.

Author: epall

lib/Computer.Build.rb

@@ -42,10 +42,6 @@ def generate
       m.signal :opcode,
         VHDL::STD_LOGIC_VECTOR((opcode_length-1)..0)
 
-      states.values.map(&:constant_value).compact.uniq.each do |const|
-        m.constant "CONSTANT_#{const}", VHDL::STD_LOGIC_VECTOR(7..0), const.to_logic(8)
-      end
-
       m.reset do |r|
         r.goto :fetch
         control_signals.each do |sig|
@@ -63,7 +59,7 @@ def generate
           s.assign :alu_operation, state.alu_op ? state.alu_op.opcode : "000"
 
           if state.constant_value
-            s.assign :system_bus, "CONSTANT_#{state.constant_value}".to_sym
+            s.assign :system_bus, state.constant_value.to_logic(8)
           else
             s.assign :system_bus, "ZZZZZZZZ"
           end

lib/computer_build/state_machine.rb

@@ -36,7 +36,6 @@ def initialize(name, body)
       @signals = []
       @states = []
       @transitions = []
-      @constants = []
       body[self]
     end
 
@@ -76,10 +75,6 @@ def transition(options)
       @transitions << Transition.new(options)
     end
 
-    def constant(*args)
-      @constants << VHDL::Constant.new(*args)
-    end
-
     def generate(out)
       representation = entity(@name) do |e|
         e.port "clock", :in, VHDL::STD_LOGIC
@@ -105,8 +100,6 @@ def generate(out)
           e.signal(*args)
         end
 
-        e.constants = @constants
-
         e.behavior do |b|
           b.process [:clock, :reset, :state] do |p|
             if @reset

lib/computer_build/vhdl.rb

@@ -78,7 +78,6 @@ def initialize(name, body)
       @signals = []
       @types = []
       @components = []
-      @constants = []
       body[self]
     end
 
@@ -103,10 +102,6 @@ def component(*args, &body)
       @components << Component.new(*args, &body)
     end
 
-    def constants=(consts)
-      @constants = consts
-    end
-
     def generate(out=$stdout)
       out.puts "ENTITY #{@name} IS"
       out.puts "PORT("
@@ -119,7 +114,6 @@ def generate(out=$stdout)
       @types.each {|t| t.generate(out, 1)}
       @signals.each {|t| t.generate(out, 1)}
       @components.each {|c| c.generate(out, 1)}
-      @constants.each {|c| c.generate(out, 1)}
       out.puts "BEGIN"
       @behavior.generate(out, 1)
       out.puts "END arch_#{@name};"
@@ -193,18 +187,6 @@ def line
     end
   end
 
-  class Constant < SingleLineStatement
-    def initialize(name, type, value)
-      @name = name
-      @type = type
-      @value = value
-    end
-
-    def line
-      "CONSTANT #{@name} : #{@type} := #{quoted(@value)};"
-    end
-  end
-
   class Behavior
     include StatementBlock
 

src/computer_build.clj

@@ -10,6 +10,19 @@
 (defn wr [port]
   (keyword (str "wr_" (name port))))
 
+(defn binary* [accumulator num]
+  (let [last-bit (if (even? num) "0" "1")]
+    (cond
+      (= 0 num) (str "0" accumulator)
+      (= 1 num) (str "1" accumulator)
+      true (recur (str last-bit accumulator) (int (/ num 2))))))
+
+(defn binary [width num]
+  "Convert number to binary literal format expected in VHDL"
+  (let [value (binary* "" num)
+        length (count value)]
+    (str (apply str (repeat (- width length) "0")) value)))
+
 (defn alu-op-to-opcode [op]
   (if op
     (cond
@@ -56,7 +69,7 @@
 (defn make-states-for-instruction [[_ instruction-name & RTLs]]
   (let [microcode (flatten-1 (map rtl-to-microcode RTLs))
         last-index (- (count microcode) 1)
-        make-state (fn [body index]
+        link-state (fn [body index]
                      {(name-for-state instruction-name index)
                       ; add next state to instruction body
                       (assoc body
@@ -68,7 +81,7 @@
                                (name-for-state
                                  instruction-name
                                  (+ index 1))))})]
-    (apply merge (map make-state microcode (iterate inc 0)))))
+    (apply merge (map link-state microcode (iterate inc 0)))))
 
 (defn make-states [instructions]
   "Given a set of instructions, create the set of states
@@ -94,6 +107,9 @@
            (:code state)
            assertions
            clears
+           (if-let [const (:constant-value state)]
+             `((<= :system_bus ~(binary 8 const)))
+             `((<= :system_bus ~(apply str (repeat 8 "Z")))))
            `((<= :alu_operation ~(alu-op-to-opcode (:alu_op state))))))))
 
 (defn control-unit [instructions]
@@ -115,7 +131,7 @@
         control-signals (set (apply concat (map
                                              (fn [[_ body]] (:control-signals body))
                                              states)))
-        inputs {:reset std-logic :system_bus (std-logic-vector 7 0)}
+        inputs {:reset std-logic}
         outputs (assoc
                   (zipmap control-signals (repeat (count control-signals) std-logic))
                   :alu_operation (std-logic-vector 2 0))]
@@ -125,11 +141,14 @@
                inputs
                ; outputs
                outputs
+               ; input/outputs
+               {:system_bus (std-logic-vector 7 0)}
                ; signals
                { :opcode (std-logic-vector (- opcode-width 1) 0) }
                ; reset
                (list* '(<= :alu_operation "000")
                       '(goto :fetch)
+                      '(<= :system_bus "ZZZZZZZZ")
                       (map #(list 'low %) control-signals))
                ; states
                (mapmap (partial realize-state control-signals) states)
@@ -216,7 +235,9 @@
             (:rd :in ~std-logic))
 
           (component :control_unit
-            ~@(concat (map input control-in) (map output control-out)))
+            ~@(concat (map input control-in)
+                      (map output control-out)
+                      `((:system_bus :inout ~(std-logic-vector 7 0)))))
             ]
           ; architecture
           [
@@ -232,6 +253,6 @@
                     :wr_alu_a :wr_alu_b :rd_alu)
           (instance :control_unit "control0"
                     ; same ports as the control signals we got
-                    ~@(map first (concat control-in control-out)))
+                    ~@(map first (concat control-in control-out)) :system_bus)
           (<= :bus_inspection :system_bus)
           ]))))))

src/computer_build/state_machine.clj

@@ -32,15 +32,16 @@
             ~(second transition))
      [(<= ~state-variable ~(state-from-name (last transition)))])))
 
-(defn state-machine [name inputs outputs signals reset states transitions]
+(defn state-machine [name inputs outputs inouts signals reset states transitions]
 	"Create a state machine that operates from the given inputs, triggering
 	the specified transitions to the listed states that generate outputs on
 	the signals in the outputs array"
   (let [inports (reformat-ports inputs :in)
-        outports (reformat-ports outputs :out)]
+        outports (reformat-ports outputs :out)
+        inoutports (reformat-ports inouts :inout)]
 	`(entity ~name
           ; Ports
-          ~(concat ['(:clock :in "std_logic")] inports outports)
+          ~(concat ['(:clock :in "std_logic")] inports outports inoutports)
           ; Definitions
           ((deftype "STATE_TYPE"
                     ~(map #(str "state_" (keyword-to-str %)) (keys states)))