Skip to content

Commit 16c66b6

Browse files
jakubcabaljakubcabal
committed
EXAMPLES [FEATURE]: Add new Spirit Level example design for CYC1000 board
1 parent e09836c commit 16c66b6

File tree

4 files changed

+252
-0
lines changed

4 files changed

+252
-0
lines changed

‎examples/spirit_level/quartus/spirit_level_cyc1000.qpf

+9
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
#-------------------------------------------------------------------------------
2+
# PROJECT: SIMPLE UART FOR FPGA
3+
#-------------------------------------------------------------------------------
4+
# AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
5+
# LICENSE: The MIT License, please read LICENSE file
6+
# WEBSITE: https://github.com/jakubcabal/uart-for-fpga
7+
#-------------------------------------------------------------------------------
8+
9+
PROJECT_REVISION = "UART_LOOPBACK_CYC1000"

‎examples/spirit_level/quartus/spirit_level_cyc1000.qsf

+38
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,38 @@
1+
#-------------------------------------------------------------------------------
2+
# PROJECT: SPI MASTER AND SLAVE FOR FPGA
3+
#-------------------------------------------------------------------------------
4+
# AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
5+
# LICENSE: The MIT License, please read LICENSE file
6+
# WEBSITE: https://github.com/jakubcabal/spi-fpga
7+
#-------------------------------------------------------------------------------
8+
9+
# QUARTUS SETTINGS FILE FOR CYC1000 BOARD
10+
set_global_assignment -name FAMILY "Cyclone 10 LP"
11+
set_global_assignment -name DEVICE 10CL025YU256C8G
12+
set_global_assignment -name TOP_LEVEL_ENTITY SPIRIT_LEVEL_CYC1000
13+
14+
# PROJECT VHDL FILES
15+
set_global_assignment -name VHDL_FILE ../../../rtl/spi_master.vhd
16+
set_global_assignment -name VHDL_FILE ../../common/rst_sync.vhd
17+
set_global_assignment -name VHDL_FILE ../spirit_level_cyc1000.vhd
18+
19+
# TIMING CONSTRAINTS
20+
set_global_assignment -name SDC_FILE ./spirit_level_cyc1000.sdc
21+
22+
# FPGA PINS ASSIGNMENT
23+
set_location_assignment PIN_M2 -to CLK_12M
24+
set_location_assignment PIN_N6 -to RST_BTN_N
25+
26+
set_location_assignment PIN_F3 -to SCLK
27+
set_location_assignment PIN_D1 -to CS_N
28+
set_location_assignment PIN_G2 -to MOSI
29+
set_location_assignment PIN_G1 -to MISO
30+
31+
set_location_assignment PIN_M6 -to USER_LEDS[0]
32+
set_location_assignment PIN_T4 -to USER_LEDS[1]
33+
set_location_assignment PIN_T3 -to USER_LEDS[2]
34+
set_location_assignment PIN_R3 -to USER_LEDS[3]
35+
set_location_assignment PIN_T2 -to USER_LEDS[4]
36+
set_location_assignment PIN_R4 -to USER_LEDS[5]
37+
set_location_assignment PIN_N5 -to USER_LEDS[6]
38+
set_location_assignment PIN_N3 -to USER_LEDS[7]

‎examples/spirit_level/quartus/spirit_level_cyc1000.sdc

+9
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
#-------------------------------------------------------------------------------
2+
# PROJECT: SPI MASTER AND SLAVE FOR FPGA
3+
#-------------------------------------------------------------------------------
4+
# AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
5+
# LICENSE: The MIT License, please read LICENSE file
6+
# WEBSITE: https://github.com/jakubcabal/spi-fpga
7+
#-------------------------------------------------------------------------------
8+
9+
create_clock -name CLK12M -period 12MHz [get_ports {CLK_12M}]

‎examples/spirit_level/spirit_level_cyc1000.vhd

+196
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,196 @@
1+
--------------------------------------------------------------------------------
2+
-- PROJECT: SPI MASTER AND SLAVE FOR FPGA
3+
--------------------------------------------------------------------------------
4+
-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
5+
-- LICENSE: The MIT License, please read LICENSE file
6+
-- WEBSITE: https://github.com/jakubcabal/spi-fpga
7+
--------------------------------------------------------------------------------
8+
9+
library IEEE;
10+
use IEEE.STD_LOGIC_1164.ALL;
11+
use IEEE.NUMERIC_STD.ALL;
12+
13+
entity SPIRIT_LEVEL_CYC1000 is
14+
Port (
15+
CLK_12M : in std_logic; -- system clock 12 MHz
16+
RST_BTN_N : in std_logic; -- low active reset button
17+
-- SPI MASTER INTERFACE TO LIS3DH SENSOR
18+
SCLK : out std_logic;
19+
CS_N : out std_logic;
20+
MOSI : out std_logic;
21+
MISO : in std_logic;
22+
-- USER LEDS
23+
USER_LEDS : out std_logic_vector(8-1 downto 0)
24+
);
25+
end entity;
26+
27+
architecture RTL of SPIRIT_LEVEL_CYC1000 is
28+
29+
signal rst_btn : std_logic;
30+
signal reset : std_logic;
31+
32+
signal spi_din : std_logic_vector(8-1 downto 0);
33+
signal spi_din_last : std_logic;
34+
signal spi_din_vld : std_logic;
35+
signal spi_din_rdy : std_logic;
36+
signal spi_dout : std_logic_vector(8-1 downto 0);
37+
signal spi_dout_vld : std_logic;
38+
39+
type state is (cfg1_addr, cfg1_wr, out_addr, out_rd, out_do);
40+
signal fsm_pstate : state;
41+
signal fsm_nstate : state;
42+
43+
signal sensor_wr : std_logic;
44+
signal sensor_data : std_logic_vector(8-1 downto 0);
45+
signal sensor_sigd : signed(8-1 downto 0);
46+
47+
begin
48+
49+
rst_btn <= not RST_BTN_N;
50+
51+
rst_sync_i : entity work.RST_SYNC
52+
port map (
53+
CLK => CLK_12M,
54+
ASYNC_RST => rst_btn,
55+
SYNCED_RST => reset
56+
);
57+
58+
spi_master_i : entity work.SPI_MASTER
59+
generic map(
60+
CLK_FREQ => 12e6,
61+
SCLK_FREQ => 1e6,
62+
SLAVE_COUNT => 1
63+
)
64+
port map (
65+
CLK => CLK_12M,
66+
RST => reset,
67+
-- SPI MASTER INTERFACE
68+
SCLK => SCLK,
69+
CS_N(0) => CS_N,
70+
MOSI => MOSI,
71+
MISO => MISO,
72+
-- USER INTERFACE
73+
DIN_ADDR => (others => '0'),
74+
DIN => spi_din,
75+
DIN_LAST => spi_din_last,
76+
DIN_VLD => spi_din_vld,
77+
DIN_RDY => spi_din_rdy,
78+
DOUT => spi_dout,
79+
DOUT_VLD => spi_dout_vld
80+
);
81+
82+
-- -------------------------------------------------------------------------
83+
-- FSM
84+
-- -------------------------------------------------------------------------
85+
86+
process (CLK_12M)
87+
begin
88+
if (rising_edge(CLK_12M)) then
89+
if (reset = '1') then
90+
fsm_pstate <= cfg1_addr;
91+
else
92+
fsm_pstate <= fsm_nstate;
93+
end if;
94+
end if;
95+
end process;
96+
97+
process (fsm_pstate, spi_din_rdy, spi_dout_vld)
98+
begin
99+
fsm_nstate <= fsm_pstate;
100+
spi_din <= (others => '0');
101+
spi_din_last <= '0';
102+
spi_din_vld <= '0';
103+
sensor_wr <= '0';
104+
105+
case fsm_pstate is
106+
when cfg1_addr =>
107+
spi_din <= "00100000";
108+
spi_din_vld <= '1';
109+
if (spi_din_rdy = '1') then
110+
fsm_nstate <= cfg1_wr;
111+
end if;
112+
113+
when cfg1_wr =>
114+
spi_din <= X"37";
115+
spi_din_vld <= '1';
116+
spi_din_last <= '1';
117+
if (spi_din_rdy = '1') then
118+
fsm_nstate <= out_addr;
119+
end if;
120+
121+
when out_addr =>
122+
spi_din <= "10101001";
123+
spi_din_vld <= '1';
124+
if (spi_din_rdy = '1') then
125+
fsm_nstate <= out_rd;
126+
end if;
127+
128+
when out_rd =>
129+
spi_din_vld <= '1';
130+
spi_din_last <= '1';
131+
if (spi_din_rdy = '1') then
132+
fsm_nstate <= out_do;
133+
end if;
134+
135+
when out_do =>
136+
if (spi_dout_vld = '1') then
137+
sensor_wr <= '1';
138+
fsm_nstate <= out_addr;
139+
end if;
140+
end case;
141+
end process;
142+
143+
-- -------------------------------------------------------------------------
144+
-- SENSOR DATA REGISTER
145+
-- -------------------------------------------------------------------------
146+
147+
process (CLK_12M)
148+
begin
149+
if (rising_edge(CLK_12M)) then
150+
if (sensor_wr = '1') then
151+
sensor_data <= spi_dout;
152+
end if;
153+
end if;
154+
end process;
155+
156+
-- -------------------------------------------------------------------------
157+
-- USER LEDS LOGIC
158+
-- -------------------------------------------------------------------------
159+
160+
sensor_sigd <= signed(sensor_data);
161+
162+
process (CLK_12M)
163+
begin
164+
if (rising_edge(CLK_12M)) then
165+
USER_LEDS <= "00000000";
166+
if (sensor_sigd <= -16) then
167+
USER_LEDS <= "10000000";
168+
end if;
169+
if (sensor_sigd > -16) and (sensor_sigd <= -12) then
170+
USER_LEDS <= "01000000";
171+
end if;
172+
if (sensor_sigd > -12) and (sensor_sigd <= -8) then
173+
USER_LEDS <= "00100000";
174+
end if;
175+
if (sensor_sigd > -8) and (sensor_sigd <= -4) then
176+
USER_LEDS <= "00010000";
177+
end if;
178+
if (sensor_sigd > -4) and (sensor_sigd < 4) then
179+
USER_LEDS <= "00011000";
180+
end if;
181+
if (sensor_sigd >= 4) and (sensor_sigd < 8) then
182+
USER_LEDS <= "00001000";
183+
end if;
184+
if (sensor_sigd >= 8) and (sensor_sigd < 12) then
185+
USER_LEDS <= "00000100";
186+
end if;
187+
if (sensor_sigd >= 12) and (sensor_sigd < 16) then
188+
USER_LEDS <= "00000010";
189+
end if;
190+
if (sensor_sigd >= 16) then
191+
USER_LEDS <= "00000001";
192+
end if;
193+
end if;
194+
end process;
195+
196+
end architecture;

0 commit comments

Comments
 (0)