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[CodeGen] Add MachineRegisterClassInfo analysis pass
Which is a wrapper of `RegisterClassInfo`. This can cache the result of `RegisterClassInfo` and hence we can reduce compile time.
1 parent 66a88f6 commit 95ed02c

27 files changed

+201
-53
lines changed

‎llvm/include/llvm/CodeGen/MachinePipeliner.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@ class MachinePipeliner : public MachineFunctionPass {
7474
const MachineDominatorTree *MDT = nullptr;
7575
const InstrItineraryData *InstrItins = nullptr;
7676
const TargetInstrInfo *TII = nullptr;
77-
RegisterClassInfo RegClassInfo;
77+
RegisterClassInfo *RegClassInfo = nullptr;
7878
bool disabledByPragma = false;
7979
unsigned II_setByPragma = 0;
8080

‎llvm/include/llvm/CodeGen/MachineRegisterClassInfo.h

+57
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,57 @@
1+
//=- MachineRegisterClassInfo.h - Machine Register Class Info -----*- C++ -*-=//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
//
9+
// This analysis calculates register class info via RegisterClassInfo.
10+
//
11+
//===----------------------------------------------------------------------===//
12+
13+
#ifndef LLVM_CODEGEN_MACHINEREGISTERCLASSINFO_H
14+
#define LLVM_CODEGEN_MACHINEREGISTERCLASSINFO_H
15+
16+
#include "llvm/CodeGen/MachineFunctionPass.h"
17+
#include "llvm/CodeGen/MachinePassManager.h"
18+
#include "llvm/CodeGen/RegisterClassInfo.h"
19+
#include "llvm/Pass.h"
20+
21+
namespace llvm {
22+
23+
class MachineRegisterClassInfoAnalysis
24+
: public AnalysisInfoMixin<MachineRegisterClassInfoAnalysis> {
25+
friend AnalysisInfoMixin<MachineRegisterClassInfoAnalysis>;
26+
27+
static AnalysisKey Key;
28+
29+
public:
30+
using Result = RegisterClassInfo;
31+
32+
Result run(MachineFunction &, MachineFunctionAnalysisManager &);
33+
};
34+
35+
class MachineRegisterClassInfoWrapperPass : public MachineFunctionPass {
36+
virtual void anchor();
37+
38+
RegisterClassInfo RCI;
39+
40+
public:
41+
static char ID;
42+
43+
MachineRegisterClassInfoWrapperPass();
44+
45+
void getAnalysisUsage(AnalysisUsage &AU) const override {
46+
AU.setPreservesAll();
47+
MachineFunctionPass::getAnalysisUsage(AU);
48+
}
49+
50+
bool runOnMachineFunction(MachineFunction &MF) override;
51+
52+
RegisterClassInfo &getRCI() { return RCI; }
53+
const RegisterClassInfo &getRCI() const { return RCI; }
54+
};
55+
} // namespace llvm
56+
57+
#endif

‎llvm/include/llvm/CodeGen/MachineScheduler.h

-6
Original file line numberDiff line numberDiff line change
@@ -140,13 +140,7 @@ struct MachineSchedContext {
140140
const TargetPassConfig *PassConfig = nullptr;
141141
AAResults *AA = nullptr;
142142
LiveIntervals *LIS = nullptr;
143-
144143
RegisterClassInfo *RegClassInfo;
145-
146-
MachineSchedContext();
147-
MachineSchedContext &operator=(const MachineSchedContext &other) = delete;
148-
MachineSchedContext(const MachineSchedContext &other) = delete;
149-
virtual ~MachineSchedContext();
150144
};
151145

152146
/// MachineSchedRegistry provides a selection of available machine instruction

‎llvm/include/llvm/InitializePasses.h

+1
Original file line numberDiff line numberDiff line change
@@ -208,6 +208,7 @@ void initializeMachineOutlinerPass(PassRegistry &);
208208
void initializeMachinePipelinerPass(PassRegistry &);
209209
void initializeMachinePostDominatorTreeWrapperPassPass(PassRegistry &);
210210
void initializeMachineRegionInfoPassPass(PassRegistry &);
211+
void initializeMachineRegisterClassInfoWrapperPassPass(PassRegistry &);
211212
void initializeMachineSanitizerBinaryMetadataPass(PassRegistry &);
212213
void initializeMachineSchedulerPass(PassRegistry &);
213214
void initializeMachineSinkingPass(PassRegistry &);

‎llvm/include/llvm/Passes/MachinePassRegistry.def

+2
Original file line numberDiff line numberDiff line change
@@ -112,6 +112,8 @@ MACHINE_FUNCTION_ANALYSIS("machine-opt-remark-emitter",
112112
MachineOptimizationRemarkEmitterAnalysis())
113113
MACHINE_FUNCTION_ANALYSIS("machine-post-dom-tree",
114114
MachinePostDominatorTreeAnalysis())
115+
MACHINE_FUNCTION_ANALYSIS("machine-reg-class-info",
116+
MachineRegisterClassInfoAnalysis())
115117
MACHINE_FUNCTION_ANALYSIS("machine-trace-metrics", MachineTraceMetricsAnalysis())
116118
MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PIC))
117119
MACHINE_FUNCTION_ANALYSIS("slot-indexes", SlotIndexesAnalysis())

‎llvm/lib/CodeGen/BreakFalseDeps.cpp

+6-4
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
2020
#include "llvm/ADT/DepthFirstIterator.h"
2121
#include "llvm/CodeGen/LivePhysRegs.h"
2222
#include "llvm/CodeGen/MachineFunctionPass.h"
23+
#include "llvm/CodeGen/MachineRegisterClassInfo.h"
2324
#include "llvm/CodeGen/ReachingDefAnalysis.h"
2425
#include "llvm/CodeGen/RegisterClassInfo.h"
2526
#include "llvm/CodeGen/TargetInstrInfo.h"
@@ -38,7 +39,7 @@ class BreakFalseDeps : public MachineFunctionPass {
3839
MachineFunction *MF = nullptr;
3940
const TargetInstrInfo *TII = nullptr;
4041
const TargetRegisterInfo *TRI = nullptr;
41-
RegisterClassInfo RegClassInfo;
42+
RegisterClassInfo *RegClassInfo = nullptr;
4243

4344
/// List of undefined register reads in this block in forward order.
4445
std::vector<std::pair<MachineInstr *, unsigned>> UndefReads;
@@ -58,6 +59,7 @@ class BreakFalseDeps : public MachineFunctionPass {
5859
void getAnalysisUsage(AnalysisUsage &AU) const override {
5960
AU.setPreservesAll();
6061
AU.addRequired<ReachingDefAnalysis>();
62+
AU.addRequired<MachineRegisterClassInfoWrapperPass>();
6163
MachineFunctionPass::getAnalysisUsage(AU);
6264
}
6365

@@ -103,6 +105,7 @@ class BreakFalseDeps : public MachineFunctionPass {
103105
char BreakFalseDeps::ID = 0;
104106
INITIALIZE_PASS_BEGIN(BreakFalseDeps, DEBUG_TYPE, "BreakFalseDeps", false, false)
105107
INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
108+
INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
106109
INITIALIZE_PASS_END(BreakFalseDeps, DEBUG_TYPE, "BreakFalseDeps", false, false)
107110

108111
FunctionPass *llvm::createBreakFalseDeps() { return new BreakFalseDeps(); }
@@ -153,7 +156,7 @@ bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
153156
// max clearance or clearance higher than Pref.
154157
unsigned MaxClearance = 0;
155158
unsigned MaxClearanceReg = OriginalReg;
156-
ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
159+
ArrayRef<MCPhysReg> Order = RegClassInfo->getOrder(OpRC);
157160
for (MCPhysReg Reg : Order) {
158161
unsigned Clearance = RDA->getClearance(MI, Reg);
159162
if (Clearance <= MaxClearance)
@@ -285,8 +288,7 @@ bool BreakFalseDeps::runOnMachineFunction(MachineFunction &mf) {
285288
TII = MF->getSubtarget().getInstrInfo();
286289
TRI = MF->getSubtarget().getRegisterInfo();
287290
RDA = &getAnalysis<ReachingDefAnalysis>();
288-
289-
RegClassInfo.runOnMachineFunction(mf);
291+
RegClassInfo = &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
290292

291293
LLVM_DEBUG(dbgs() << "********** BREAK FALSE DEPENDENCIES **********\n");
292294

‎llvm/lib/CodeGen/CMakeLists.txt

+1
Original file line numberDiff line numberDiff line change
@@ -141,6 +141,7 @@ add_llvm_component_library(LLVMCodeGen
141141
MachinePipeliner.cpp
142142
MachinePostDominators.cpp
143143
MachineRegionInfo.cpp
144+
MachineRegisterClassInfo.cpp
144145
MachineRegisterInfo.cpp
145146
MachineScheduler.cpp
146147
MachineSink.cpp

‎llvm/lib/CodeGen/MachineCombiner.cpp

+6-3
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
#include "llvm/CodeGen/MachineFunction.h"
2020
#include "llvm/CodeGen/MachineFunctionPass.h"
2121
#include "llvm/CodeGen/MachineLoopInfo.h"
22+
#include "llvm/CodeGen/MachineRegisterClassInfo.h"
2223
#include "llvm/CodeGen/MachineRegisterInfo.h"
2324
#include "llvm/CodeGen/MachineSizeOpts.h"
2425
#include "llvm/CodeGen/MachineTraceMetrics.h"
@@ -73,7 +74,7 @@ class MachineCombiner : public MachineFunctionPass {
7374
MachineTraceMetrics::Ensemble *TraceEnsemble = nullptr;
7475
MachineBlockFrequencyInfo *MBFI = nullptr;
7576
ProfileSummaryInfo *PSI = nullptr;
76-
RegisterClassInfo RegClassInfo;
77+
RegisterClassInfo *RegClassInfo = nullptr;
7778

7879
TargetSchedModel TSchedModel;
7980

@@ -131,6 +132,7 @@ INITIALIZE_PASS_BEGIN(MachineCombiner, DEBUG_TYPE,
131132
"Machine InstCombiner", false, false)
132133
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
133134
INITIALIZE_PASS_DEPENDENCY(MachineTraceMetricsWrapperPass)
135+
INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
134136
INITIALIZE_PASS_END(MachineCombiner, DEBUG_TYPE, "Machine InstCombiner",
135137
false, false)
136138

@@ -143,6 +145,7 @@ void MachineCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
143145
AU.addPreserved<MachineTraceMetricsWrapperPass>();
144146
AU.addRequired<LazyMachineBlockFrequencyInfoPass>();
145147
AU.addRequired<ProfileSummaryInfoWrapperPass>();
148+
AU.addRequired<MachineRegisterClassInfoWrapperPass>();
146149
MachineFunctionPass::getAnalysisUsage(AU);
147150
}
148151

@@ -571,7 +574,7 @@ bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) {
571574
bool OptForSize = llvm::shouldOptimizeForSize(MBB, PSI, MBFI);
572575

573576
bool DoRegPressureReduce =
574-
TII->shouldReduceRegisterPressure(MBB, &RegClassInfo);
577+
TII->shouldReduceRegisterPressure(MBB, RegClassInfo);
575578

576579
while (BlockIter != MBB->end()) {
577580
auto &MI = *BlockIter++;
@@ -730,7 +733,7 @@ bool MachineCombiner::runOnMachineFunction(MachineFunction &MF) {
730733
&getAnalysis<LazyMachineBlockFrequencyInfoPass>().getBFI() :
731734
nullptr;
732735
TraceEnsemble = nullptr;
733-
RegClassInfo.runOnMachineFunction(MF);
736+
RegClassInfo = &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
734737

735738
LLVM_DEBUG(dbgs() << getPassName() << ": " << MF.getName() << '\n');
736739
if (!TII->useMachineCombiner()) {

‎llvm/lib/CodeGen/MachineLICM.cpp

+1
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,7 @@
3333
#include "llvm/CodeGen/MachineLoopInfo.h"
3434
#include "llvm/CodeGen/MachineMemOperand.h"
3535
#include "llvm/CodeGen/MachineOperand.h"
36+
#include "llvm/CodeGen/MachineRegisterClassInfo.h"
3637
#include "llvm/CodeGen/MachineRegisterInfo.h"
3738
#include "llvm/CodeGen/PseudoSourceValue.h"
3839
#include "llvm/CodeGen/TargetInstrInfo.h"

‎llvm/lib/CodeGen/MachinePipeliner.cpp

+7-3
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,7 @@
5858
#include "llvm/CodeGen/MachineLoopInfo.h"
5959
#include "llvm/CodeGen/MachineMemOperand.h"
6060
#include "llvm/CodeGen/MachineOperand.h"
61+
#include "llvm/CodeGen/MachineRegisterClassInfo.h"
6162
#include "llvm/CodeGen/MachineRegisterInfo.h"
6263
#include "llvm/CodeGen/ModuloSchedule.h"
6364
#include "llvm/CodeGen/Register.h"
@@ -234,6 +235,7 @@ INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
234235
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
235236
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
236237
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
238+
INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
237239
INITIALIZE_PASS_END(MachinePipeliner, DEBUG_TYPE,
238240
"Modulo Software Pipelining", false, false)
239241

@@ -263,8 +265,8 @@ bool MachinePipeliner::runOnMachineFunction(MachineFunction &mf) {
263265
MLI = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
264266
MDT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
265267
ORE = &getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE();
268+
RegClassInfo = &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
266269
TII = MF->getSubtarget().getInstrInfo();
267-
RegClassInfo.runOnMachineFunction(*MF);
268270

269271
for (const auto &L : *MLI)
270272
scheduleLoop(*L);
@@ -471,7 +473,7 @@ bool MachinePipeliner::swingModuloScheduler(MachineLoop &L) {
471473
assert(L.getBlocks().size() == 1 && "SMS works on single blocks only.");
472474

473475
SwingSchedulerDAG SMS(
474-
*this, L, getAnalysis<LiveIntervalsWrapperPass>().getLIS(), RegClassInfo,
476+
*this, L, getAnalysis<LiveIntervalsWrapperPass>().getLIS(), *RegClassInfo,
475477
II_setByPragma, LI.LoopPipelinerInfo.get());
476478

477479
MachineBasicBlock *MBB = L.getHeader();
@@ -503,6 +505,7 @@ void MachinePipeliner::getAnalysisUsage(AnalysisUsage &AU) const {
503505
AU.addRequired<LiveIntervalsWrapperPass>();
504506
AU.addRequired<MachineOptimizationRemarkEmitterPass>();
505507
AU.addRequired<TargetPassConfig>();
508+
AU.addRequired<MachineRegisterClassInfoWrapperPass>();
506509
MachineFunctionPass::getAnalysisUsage(AU);
507510
}
508511

@@ -514,7 +517,8 @@ bool MachinePipeliner::runWindowScheduler(MachineLoop &L) {
514517
Context.PassConfig = &getAnalysis<TargetPassConfig>();
515518
Context.AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
516519
Context.LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
517-
Context.RegClassInfo->runOnMachineFunction(*MF);
520+
Context.RegClassInfo =
521+
&getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
518522
WindowScheduler WS(&Context, L);
519523
return WS.run();
520524
}

‎llvm/lib/CodeGen/MachineRegisterClassInfo.cpp

+50
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,50 @@
1+
//===- MachineRegisterClassInfo.cpp - Machine Register Class Info ---------===//
2+
//
3+
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4+
// See https://llvm.org/LICENSE.txt for license information.
5+
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6+
//
7+
//===----------------------------------------------------------------------===//
8+
//
9+
// This analysis calculates register class info via RegisterClassInfo.
10+
//
11+
//===----------------------------------------------------------------------===//
12+
13+
#include "llvm/CodeGen/MachineRegisterClassInfo.h"
14+
#include "llvm/CodeGen/RegisterClassInfo.h"
15+
#include "llvm/InitializePasses.h"
16+
17+
using namespace llvm;
18+
19+
INITIALIZE_PASS_BEGIN(MachineRegisterClassInfoWrapperPass,
20+
"machine-reg-class-info",
21+
"Machine Register Class Info Analysis", false, true)
22+
INITIALIZE_PASS_END(MachineRegisterClassInfoWrapperPass,
23+
"machine-reg-class-info",
24+
"Machine Register Class Info Analysis", false, true)
25+
26+
MachineRegisterClassInfoAnalysis::Result
27+
MachineRegisterClassInfoAnalysis::run(MachineFunction &MF,
28+
MachineFunctionAnalysisManager &) {
29+
RegisterClassInfo RCI;
30+
RCI.runOnMachineFunction(MF);
31+
return RCI;
32+
}
33+
34+
char MachineRegisterClassInfoWrapperPass::ID = 0;
35+
36+
MachineRegisterClassInfoWrapperPass::MachineRegisterClassInfoWrapperPass()
37+
: MachineFunctionPass(ID), RCI() {
38+
PassRegistry &Registry = *PassRegistry::getPassRegistry();
39+
initializeMachineRegisterClassInfoWrapperPassPass(Registry);
40+
}
41+
42+
bool MachineRegisterClassInfoWrapperPass::runOnMachineFunction(
43+
MachineFunction &MF) {
44+
RCI.runOnMachineFunction(MF);
45+
return false;
46+
}
47+
48+
void MachineRegisterClassInfoWrapperPass::anchor() {}
49+
50+
AnalysisKey MachineRegisterClassInfoAnalysis::Key;

‎llvm/lib/CodeGen/MachineScheduler.cpp

+4-9
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@
3131
#include "llvm/CodeGen/MachineLoopInfo.h"
3232
#include "llvm/CodeGen/MachineOperand.h"
3333
#include "llvm/CodeGen/MachinePassRegistry.h"
34+
#include "llvm/CodeGen/MachineRegisterClassInfo.h"
3435
#include "llvm/CodeGen/MachineRegisterInfo.h"
3536
#include "llvm/CodeGen/RegisterClassInfo.h"
3637
#include "llvm/CodeGen/RegisterPressure.h"
@@ -205,14 +206,6 @@ void ScheduleDAGMutation::anchor() {}
205206
// Machine Instruction Scheduling Pass and Registry
206207
//===----------------------------------------------------------------------===//
207208

208-
MachineSchedContext::MachineSchedContext() {
209-
RegClassInfo = new RegisterClassInfo();
210-
}
211-
212-
MachineSchedContext::~MachineSchedContext() {
213-
delete RegClassInfo;
214-
}
215-
216209
namespace {
217210

218211
/// Base class for a machine scheduler class that can run at any point.
@@ -287,6 +280,7 @@ void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const {
287280
AU.addPreserved<SlotIndexesWrapperPass>();
288281
AU.addRequired<LiveIntervalsWrapperPass>();
289282
AU.addPreserved<LiveIntervalsWrapperPass>();
283+
AU.addRequired<MachineRegisterClassInfoWrapperPass>();
290284
MachineFunctionPass::getAnalysisUsage(AU);
291285
}
292286

@@ -299,6 +293,7 @@ INITIALIZE_PASS_BEGIN(PostMachineScheduler, "postmisched",
299293
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
300294
INITIALIZE_PASS_DEPENDENCY(MachineLoopInfoWrapperPass)
301295
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
296+
INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
302297
INITIALIZE_PASS_END(PostMachineScheduler, "postmisched",
303298
"PostRA Machine Instruction Scheduler", false, false)
304299

@@ -455,7 +450,7 @@ bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
455450
LLVM_DEBUG(LIS->dump());
456451
MF->verify(this, "Before machine scheduling.", &errs());
457452
}
458-
RegClassInfo->runOnMachineFunction(*MF);
453+
RegClassInfo = &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
459454

460455
// Instantiate the selected scheduler for this target, function, and
461456
// optimization level.

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