@@ -28,10 +28,7 @@ define <16 x i8> @widen_shuffle_mask_v16i8_to_v4i32(<16 x i8> %a, <16 x i8> %b)
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define <16 x i8 > @widen_shuffle_mask_v16i8_to_v2i64 (<16 x i8 > %a , <16 x i8 > %b ) {
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; CHECK-LABEL: widen_shuffle_mask_v16i8_to_v2i64:
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; CHECK: # %bb.0:
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- ; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI2_0)
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- ; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI2_0)
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- ; CHECK-NEXT: vshuf.d $vr2, $vr1, $vr0
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- ; CHECK-NEXT: vori.b $vr0, $vr2, 0
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+ ; CHECK-NEXT: vshuf4i.d $vr0, $vr1, 12
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; CHECK-NEXT: ret
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%r = shufflevector <16 x i8 > %a , <16 x i8 > %b , <16 x i32 > <i32 0 , i32 1 , i32 2 , i32 3 , i32 4 , i32 5 , i32 6 , i32 7 , i32 24 , i32 25 , i32 26 , i32 27 , i32 28 , i32 29 , i32 30 , i32 31 >
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ret <16 x i8 > %r
@@ -52,10 +49,7 @@ define <8 x i16> @widen_shuffle_mask_v8i16_to_v4i32(<8 x i16> %a, <8 x i16> %b)
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define <8 x i16 > @widen_shuffle_mask_v8i16_to_v2i64 (<8 x i16 > %a , <8 x i16 > %b ) {
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; CHECK-LABEL: widen_shuffle_mask_v8i16_to_v2i64:
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; CHECK: # %bb.0:
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- ; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI4_0)
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- ; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI4_0)
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- ; CHECK-NEXT: vshuf.d $vr2, $vr1, $vr0
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- ; CHECK-NEXT: vori.b $vr0, $vr2, 0
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+ ; CHECK-NEXT: vshuf4i.d $vr0, $vr1, 12
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; CHECK-NEXT: ret
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%r = shufflevector <8 x i16 > %a , <8 x i16 > %b , <8 x i32 > <i32 0 , i32 1 , i32 2 , i32 3 , i32 12 , i32 13 , i32 14 , i32 15 >
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ret <8 x i16 > %r
@@ -64,10 +58,7 @@ define <8 x i16> @widen_shuffle_mask_v8i16_to_v2i64(<8 x i16> %a, <8 x i16> %b)
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define <4 x i32 > @widen_shuffle_mask_v4i32_to_v2i64 (<4 x i32 > %a , <4 x i32 > %b ) {
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; CHECK-LABEL: widen_shuffle_mask_v4i32_to_v2i64:
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; CHECK: # %bb.0:
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- ; CHECK-NEXT: pcalau12i $a0, %pc_hi20(.LCPI5_0)
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- ; CHECK-NEXT: vld $vr2, $a0, %pc_lo12(.LCPI5_0)
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- ; CHECK-NEXT: vshuf.d $vr2, $vr1, $vr0
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- ; CHECK-NEXT: vori.b $vr0, $vr2, 0
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+ ; CHECK-NEXT: vshuf4i.d $vr0, $vr1, 12
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; CHECK-NEXT: ret
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%r = shufflevector <4 x i32 > %a , <4 x i32 > %b , <4 x i32 > <i32 0 , i32 1 , i32 6 , i32 7 >
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ret <4 x i32 > %r
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