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Mikhail Gudim
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[CFIInstrInserter] Tests for scenarios not currently handled by
`CFIInstrInserter`. We add an option to enable `CFIInstrInserter` on RISCV (`false` by default). On RISCV there exists a realistic scenario (involing scalable vectors) where we need CFIInstrInserter to handle `cfi_escape`. We add a test for that. Also, we add a test for the scenario when a callee-saved register is saved at different locations.
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‎llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2239,3 +2239,12 @@ void RISCVFrameLowering::inlineStackProbe(MachineFunction &MF,
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}
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}
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}
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int RISCVFrameLowering::getInitialCFAOffset(const MachineFunction &MF) const {
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return 0;
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}
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Register
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RISCVFrameLowering::getInitialCFARegister(const MachineFunction &MF) const {
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return RISCV::X2;
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}

‎llvm/lib/Target/RISCV/RISCVFrameLowering.h

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@@ -112,6 +112,8 @@ class RISCVFrameLowering : public TargetFrameLowering {
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const DebugLoc &DL, int64_t Amount,
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MachineInstr::MIFlag Flag, bool EmitCFI,
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bool DynAllocation) const;
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int getInitialCFAOffset(const MachineFunction &MF) const override;
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Register getInitialCFARegister(const MachineFunction &MF) const override;
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};
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} // namespace llvm
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#endif

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 12 additions & 1 deletion
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@@ -117,6 +117,11 @@ static cl::opt<bool>
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cl::desc("Enable Machine Pipeliner for RISC-V"),
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cl::init(false), cl::Hidden);
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static cl::opt<bool> EnableCFIInstrInserter(
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"riscv-enable-cfi-instr-inserter",
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cl::desc("Enable CFI Instruction Inserter for RISC-V"), cl::init(false),
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cl::Hidden);
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
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RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
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RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
@@ -187,7 +192,10 @@ RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
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if (TT.isOSFuchsia() && !TT.isArch64Bit())
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report_fatal_error("Fuchsia is only supported for 64-bit");
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setCFIFixup(true);
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if (EnableCFIInstrInserter)
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setCFIFixup(false);
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else
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setCFIFixup(true);
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}
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const RISCVSubtarget *
@@ -584,6 +592,9 @@ void RISCVPassConfig::addPreEmitPass2() {
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addPass(createUnpackMachineBundles([&](const MachineFunction &MF) {
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return MF.getFunction().getParent()->getModuleFlag("kcfi");
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}));
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if (EnableCFIInstrInserter)
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addPass(createCFIInstrInserter());
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}
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void RISCVPassConfig::addMachineSSAOptimization() {

‎llvm/test/CodeGen/RISCV/cfi-escape.mir

Lines changed: 88 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,88 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc %s -mtriple=riscv64 -mattr=+v \
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# RUN: -run-pass=prologepilog,cfi-instr-inserter \
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# RUN: -riscv-enable-cfi-instr-inserter=true \
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# RUN: | FileCheck %s
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#
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# In this test prolog will be inserted in bb.3. We need to save the scalable vector register v1.
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# This will emit cfi_escape in bb.3. We need to emit the same cfi_escape in the begining of bb.2.
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# Currently, CFIInstrInserter doesn't handle escape, so we have wrong cfi in this example.
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--- |
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define riscv_vector_cc void @test0(ptr %p0, ptr %p1) #0 {
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entry:
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%v = load <4 x i32>, ptr %p0, align 16
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store <4 x i32> %v, ptr %p1, align 16
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ret void
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}
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attributes #0 = { "target-features"="+v" }
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...
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---
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name: test0
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tracksRegLiveness: true
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frameInfo:
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savePoint: '%bb.3'
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restorePoint: '%bb.2'
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body: |
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; CHECK-LABEL: name: test0
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; CHECK: bb.0.entry:
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; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000)
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; CHECK-NEXT: liveins: $x10, $x11, $v1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: BEQ $x10, $x0, %bb.3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: liveins: $v1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: PseudoRET
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: CFI_INSTRUCTION def_cfa_offset 16
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; CHECK-NEXT: $x10 = ADDI $x2, 16
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; CHECK-NEXT: $v1 = frame-destroy VL1RE8_V killed $x10 :: (load unknown-size from %stack.0, align 8)
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; CHECK-NEXT: $x10 = frame-destroy PseudoReadVLENB
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; CHECK-NEXT: $x2 = frame-destroy ADD $x2, killed $x10
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; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa $x2, 16
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; CHECK-NEXT: frame-destroy CFI_INSTRUCTION restore $v1
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; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 16
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; CHECK-NEXT: frame-destroy CFI_INSTRUCTION def_cfa_offset 0
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; CHECK-NEXT: PseudoBR %bb.1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: liveins: $x10, $x11, $v1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: $x2 = frame-setup ADDI $x2, -16
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16
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; CHECK-NEXT: $x12 = frame-setup PseudoReadVLENB
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; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x12
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22
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; CHECK-NEXT: $x12 = ADDI $x2, 16
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; CHECK-NEXT: frame-setup VS1R_V killed $v1, killed $x12 :: (store unknown-size into %stack.0, align 8)
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; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x10, 0x61, 0x08, 0x11, 0x7f, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22
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; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 4, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: renamable $v1 = PseudoVLE32_V_M1 undef renamable $v1, killed renamable $x10, 4, 5 /* e32 */, 2 /* tu, ma */, implicit $vl, implicit $vtype
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; CHECK-NEXT: PseudoVSE32_V_M1 killed renamable $v1, killed renamable $x11, 4, 5 /* e32 */, implicit $vl, implicit $vtype
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; CHECK-NEXT: PseudoBR %bb.2
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bb.0.entry:
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liveins: $x10, $x11
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BEQ $x10, $x0, %bb.3
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bb.1:
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PseudoRET
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bb.2:
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PseudoBR %bb.1
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bb.3:
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liveins: $x10, $x11
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dead $x0 = PseudoVSETIVLI 4, 208, implicit-def $vl, implicit-def $vtype
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renamable $v1 = PseudoVLE32_V_M1 undef renamable $v1, killed renamable $x10, 4, 5, 2, implicit $vl, implicit $vtype
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PseudoVSE32_V_M1 killed renamable $v1, killed renamable $x11, 4, 5, implicit $vl, implicit $vtype
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PseudoBR %bb.2
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...

‎llvm/test/CodeGen/RISCV/cfi-multiple-locations.mir

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,35 @@
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# RUN: llc %s -mtriple=riscv64 \
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# RUN: -run-pass=cfi-instr-inserter \
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# RUN: -riscv-enable-cfi-instr-inserter=true \
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# RUN: | FileCheck %s
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# XFAIL: *
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# Technically, it is possible that the a callee-saved register is saved in different locations.
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# CFIInstrInserter should handle this, but currently it does not.
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---
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name: multiple_locations
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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liveins: $x10, $x9, $x2
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BEQ $x10, $x0, %bb.3
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bb.1:
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liveins: $x10, $x9, $x2
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$x5 = COPY $x9
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CFI_INSTRUCTION register $x9, $x5
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$x9 = COPY $x5
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CFI_INSTRUCTION register $x9, $x9
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PseudoBR %bb.3
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bb.2:
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liveins: $x10, $x9, $x2
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SD $x10, $x2, 0 :: (store (s64))
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CFI_INSTRUCTION offset $x9, 0
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$x10 = LD $x2, 0 :: (load (s64))
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CFI_INSTRUCTION register $x9, $x9
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PseudoBR %bb.1
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bb.3:
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PseudoRET
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...

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