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[CodeGen] Add MachineRegisterClassInfo analysis pass
Which is a wrapper of `RegisterClassInfo`. This can cache the result of `RegisterClassInfo` and hence we can reduce compile time.
1 parent f421a7a commit f4a57a0

15 files changed

+130
-4
lines changed

‎llvm/include/llvm/CodeGen/MachineRegisterClassInfo.h

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@@ -0,0 +1,57 @@
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//=- MachineRegisterClassInfo.h - Machine Register Class Info -----*- C++ -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This analysis calculates register class info via RegisterClassInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEREGISTERCLASSINFO_H
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#define LLVM_CODEGEN_MACHINEREGISTERCLASSINFO_H
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachinePassManager.h"
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#include "llvm/CodeGen/RegisterClassInfo.h"
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#include "llvm/Pass.h"
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namespace llvm {
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class MachineRegisterClassInfoAnalysis
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: public AnalysisInfoMixin<MachineRegisterClassInfoAnalysis> {
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friend AnalysisInfoMixin<MachineRegisterClassInfoAnalysis>;
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static AnalysisKey Key;
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public:
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using Result = RegisterClassInfo;
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Result run(MachineFunction &, MachineFunctionAnalysisManager &);
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};
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class MachineRegisterClassInfoWrapperPass : public MachineFunctionPass {
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virtual void anchor();
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RegisterClassInfo RCI;
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public:
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static char ID;
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MachineRegisterClassInfoWrapperPass();
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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RegisterClassInfo &getRCI() { return RCI; }
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const RegisterClassInfo &getMBPI() const { return RCI; }
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};
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} // namespace llvm
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#endif

‎llvm/include/llvm/InitializePasses.h

+1
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@@ -208,6 +208,7 @@ void initializeMachineOutlinerPass(PassRegistry &);
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void initializeMachinePipelinerPass(PassRegistry &);
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void initializeMachinePostDominatorTreeWrapperPassPass(PassRegistry &);
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void initializeMachineRegionInfoPassPass(PassRegistry &);
211+
void initializeMachineRegisterClassInfoWrapperPassPass(PassRegistry &);
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void initializeMachineSanitizerBinaryMetadataPass(PassRegistry &);
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void initializeMachineSchedulerPass(PassRegistry &);
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void initializeMachineSinkingPass(PassRegistry &);

‎llvm/include/llvm/Passes/MachinePassRegistry.def

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@@ -112,6 +112,8 @@ MACHINE_FUNCTION_ANALYSIS("machine-opt-remark-emitter",
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MachineOptimizationRemarkEmitterAnalysis())
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MACHINE_FUNCTION_ANALYSIS("machine-post-dom-tree",
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MachinePostDominatorTreeAnalysis())
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MACHINE_FUNCTION_ANALYSIS("machine-reg-class-info",
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MachineRegisterClassInfoAnalysis())
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MACHINE_FUNCTION_ANALYSIS("machine-trace-metrics", MachineTraceMetricsAnalysis())
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MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PIC))
117119
MACHINE_FUNCTION_ANALYSIS("slot-indexes", SlotIndexesAnalysis())

‎llvm/lib/CodeGen/CMakeLists.txt

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Original file line numberDiff line numberDiff line change
@@ -142,6 +142,7 @@ add_llvm_component_library(LLVMCodeGen
142142
MachinePipeliner.cpp
143143
MachinePostDominators.cpp
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MachineRegionInfo.cpp
145+
MachineRegisterClassInfo.cpp
145146
MachineRegisterInfo.cpp
146147
MachineScheduler.cpp
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MachineSink.cpp

‎llvm/lib/CodeGen/MachineLICM.cpp

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@@ -33,6 +33,7 @@
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineMemOperand.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterClassInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"

‎llvm/lib/CodeGen/MachineRegisterClassInfo.cpp

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@@ -0,0 +1,50 @@
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//===- MachineRegisterClassInfo.cpp - Machine Register Class Info ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This analysis calculates register class info via RegisterClassInfo.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineRegisterClassInfo.h"
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#include "llvm/CodeGen/RegisterClassInfo.h"
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#include "llvm/InitializePasses.h"
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using namespace llvm;
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INITIALIZE_PASS_BEGIN(MachineRegisterClassInfoWrapperPass,
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"machine-reg-class-info",
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"Machine Register Class Info Analysis", false, true)
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INITIALIZE_PASS_END(MachineRegisterClassInfoWrapperPass,
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"machine-reg-class-info",
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"Machine Register Class Info Analysis", false, true)
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MachineRegisterClassInfoAnalysis::Result
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MachineRegisterClassInfoAnalysis::run(MachineFunction &MF,
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MachineFunctionAnalysisManager &) {
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RegisterClassInfo RCI;
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RCI.runOnMachineFunction(MF);
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return RCI;
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}
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char MachineRegisterClassInfoWrapperPass::ID = 0;
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MachineRegisterClassInfoWrapperPass::MachineRegisterClassInfoWrapperPass()
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: MachineFunctionPass(ID), RCI() {
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PassRegistry &Registry = *PassRegistry::getPassRegistry();
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initializeMachineRegisterClassInfoWrapperPassPass(Registry);
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}
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bool MachineRegisterClassInfoWrapperPass::runOnMachineFunction(
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MachineFunction &MF) {
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RCI.runOnMachineFunction(MF);
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return false;
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}
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void MachineRegisterClassInfoWrapperPass::anchor() {}
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AnalysisKey MachineRegisterClassInfoAnalysis::Key;

‎llvm/lib/CodeGen/MachineSink.cpp

+7-4
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@@ -38,6 +38,7 @@
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachinePostDominators.h"
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#include "llvm/CodeGen/MachineRegisterClassInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineSizeOpts.h"
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#include "llvm/CodeGen/RegisterClassInfo.h"
@@ -127,7 +128,7 @@ class MachineSinking : public MachineFunctionPass {
127128
MachineBlockFrequencyInfo *MBFI = nullptr;
128129
const MachineBranchProbabilityInfo *MBPI = nullptr;
129130
AliasAnalysis *AA = nullptr;
130-
RegisterClassInfo RegClassInfo;
131+
RegisterClassInfo *RegClassInfo = nullptr;
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132133
// Remember which edges have been considered for breaking.
133134
SmallSet<std::pair<MachineBasicBlock *, MachineBasicBlock *>, 8>
@@ -200,6 +201,7 @@ class MachineSinking : public MachineFunctionPass {
200201
AU.addRequired<MachineBranchProbabilityInfoWrapperPass>();
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AU.addPreserved<MachineCycleInfoWrapperPass>();
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AU.addPreserved<MachineLoopInfoWrapperPass>();
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AU.addRequired<MachineRegisterClassInfoWrapperPass>();
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AU.addRequired<ProfileSummaryInfoWrapperPass>();
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if (UseBlockFreqInfo)
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AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
@@ -290,6 +292,7 @@ INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass)
290292
INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfoWrapperPass)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
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INITIALIZE_PASS_DEPENDENCY(MachineCycleInfoWrapperPass)
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INITIALIZE_PASS_DEPENDENCY(MachineRegisterClassInfoWrapperPass)
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INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
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INITIALIZE_PASS_END(MachineSinking, DEBUG_TYPE, "Machine code sinking", false,
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false)
@@ -731,7 +734,7 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
731734
: nullptr;
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MBPI = &getAnalysis<MachineBranchProbabilityInfoWrapperPass>().getMBPI();
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AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
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RegClassInfo.runOnMachineFunction(MF);
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RegClassInfo = &getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
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TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>();
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EnableSinkAndFold = PassConfig->getEnableSinkAndFold();
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@@ -1068,7 +1071,7 @@ MachineSinking::getBBRegisterPressure(const MachineBasicBlock &MBB) {
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RegPressureTracker RPTracker(Pressure);
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10701073
// Initialize the register pressure tracker.
1071-
RPTracker.init(MBB.getParent(), &RegClassInfo, nullptr, &MBB, MBB.end(),
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RPTracker.init(MBB.getParent(), RegClassInfo, nullptr, &MBB, MBB.end(),
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/*TrackLaneMasks*/ false, /*TrackUntiedDefs=*/true);
10731076

10741077
for (MachineBasicBlock::const_iterator MII = MBB.instr_end(),
@@ -1098,7 +1101,7 @@ bool MachineSinking::registerPressureSetExceedsLimit(
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std::vector<unsigned> BBRegisterPressure = getBBRegisterPressure(MBB);
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for (; *PS != -1; PS++)
11001103
if (Weight + BBRegisterPressure[*PS] >=
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RegClassInfo.getRegPressureSetLimit(*PS))
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RegClassInfo->getRegPressureSetLimit(*PS))
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return true;
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return false;
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}

‎llvm/lib/Passes/PassBuilder.cpp

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@@ -116,6 +116,7 @@
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#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
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#include "llvm/CodeGen/MachinePassManager.h"
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#include "llvm/CodeGen/MachinePostDominators.h"
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#include "llvm/CodeGen/MachineRegisterClassInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/MachineTraceMetrics.h"
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#include "llvm/CodeGen/MachineVerifier.h"

‎llvm/test/CodeGen/AArch64/O3-pipeline.ll

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@@ -154,6 +154,7 @@
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; CHECK-NEXT: Machine Common Subexpression Elimination
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; CHECK-NEXT: MachinePostDominator Tree Construction
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; CHECK-NEXT: Machine Cycle Info Analysis
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; CHECK-NEXT: Machine Register Class Info Analysis
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; CHECK-NEXT: Machine code sinking
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; CHECK-NEXT: Peephole Optimizations
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; CHECK-NEXT: Remove dead machine instructions

‎llvm/test/CodeGen/AMDGPU/llc-pipeline.ll

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@@ -322,6 +322,7 @@
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; GCN-O1-NEXT: Machine Common Subexpression Elimination
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; GCN-O1-NEXT: MachinePostDominator Tree Construction
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; GCN-O1-NEXT: Machine Cycle Info Analysis
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; GCN-O1-NEXT: Machine Register Class Info Analysis
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; GCN-O1-NEXT: Machine code sinking
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; GCN-O1-NEXT: Peephole Optimizations
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; GCN-O1-NEXT: Remove dead machine instructions
@@ -622,6 +623,7 @@
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; GCN-O1-OPTS-NEXT: Machine Common Subexpression Elimination
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; GCN-O1-OPTS-NEXT: MachinePostDominator Tree Construction
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; GCN-O1-OPTS-NEXT: Machine Cycle Info Analysis
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; GCN-O1-OPTS-NEXT: Machine Register Class Info Analysis
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; GCN-O1-OPTS-NEXT: Machine code sinking
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; GCN-O1-OPTS-NEXT: Peephole Optimizations
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; GCN-O1-OPTS-NEXT: Remove dead machine instructions
@@ -935,6 +937,7 @@
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; GCN-O2-NEXT: Machine Common Subexpression Elimination
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; GCN-O2-NEXT: MachinePostDominator Tree Construction
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; GCN-O2-NEXT: Machine Cycle Info Analysis
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; GCN-O2-NEXT: Machine Register Class Info Analysis
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; GCN-O2-NEXT: Machine code sinking
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; GCN-O2-NEXT: Peephole Optimizations
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; GCN-O2-NEXT: Remove dead machine instructions
@@ -1262,6 +1265,7 @@
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; GCN-O3-NEXT: Machine Common Subexpression Elimination
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; GCN-O3-NEXT: MachinePostDominator Tree Construction
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; GCN-O3-NEXT: Machine Cycle Info Analysis
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; GCN-O3-NEXT: Machine Register Class Info Analysis
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; GCN-O3-NEXT: Machine code sinking
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; GCN-O3-NEXT: Peephole Optimizations
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; GCN-O3-NEXT: Remove dead machine instructions

‎llvm/test/CodeGen/ARM/O3-pipeline.ll

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@@ -97,6 +97,7 @@
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; CHECK-NEXT: Machine Common Subexpression Elimination
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; CHECK-NEXT: MachinePostDominator Tree Construction
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; CHECK-NEXT: Machine Cycle Info Analysis
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; CHECK-NEXT: Machine Register Class Info Analysis
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; CHECK-NEXT: Machine code sinking
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; CHECK-NEXT: Peephole Optimizations
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; CHECK-NEXT: Remove dead machine instructions

‎llvm/test/CodeGen/LoongArch/opt-pipeline.ll

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@@ -102,6 +102,7 @@
102102
; LAXX-NEXT: Machine Common Subexpression Elimination
103103
; LAXX-NEXT: MachinePostDominator Tree Construction
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; LAXX-NEXT: Machine Cycle Info Analysis
105+
; LAXX-NEXT: Machine Register Class Info Analysis
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; LAXX-NEXT: Machine code sinking
106107
; LAXX-NEXT: Peephole Optimizations
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; LAXX-NEXT: Remove dead machine instructions

‎llvm/test/CodeGen/PowerPC/O3-pipeline.ll

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@@ -121,6 +121,7 @@
121121
; CHECK-NEXT: Machine Common Subexpression Elimination
122122
; CHECK-NEXT: MachinePostDominator Tree Construction
123123
; CHECK-NEXT: Machine Cycle Info Analysis
124+
; CHECK-NEXT: Machine Register Class Info Analysis
124125
; CHECK-NEXT: Machine code sinking
125126
; CHECK-NEXT: Peephole Optimizations
126127
; CHECK-NEXT: Remove dead machine instructions

‎llvm/test/CodeGen/RISCV/O3-pipeline.ll

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@@ -110,6 +110,7 @@
110110
; CHECK-NEXT: Machine Common Subexpression Elimination
111111
; CHECK-NEXT: MachinePostDominator Tree Construction
112112
; CHECK-NEXT: Machine Cycle Info Analysis
113+
; CHECK-NEXT: Machine Register Class Info Analysis
113114
; CHECK-NEXT: Machine code sinking
114115
; CHECK-NEXT: Peephole Optimizations
115116
; CHECK-NEXT: Remove dead machine instructions

‎llvm/test/CodeGen/X86/opt-pipeline.ll

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@@ -114,6 +114,7 @@
114114
; CHECK-NEXT: Machine Common Subexpression Elimination
115115
; CHECK-NEXT: MachinePostDominator Tree Construction
116116
; CHECK-NEXT: Machine Cycle Info Analysis
117+
; CHECK-NEXT: Machine Register Class Info Analysis
117118
; CHECK-NEXT: Machine code sinking
118119
; CHECK-NEXT: Peephole Optimizations
119120
; CHECK-NEXT: Remove dead machine instructions

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