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Mikhail Gudim
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[RISCV][WIP] Let RA do the CSR saves.
We turn the problem of saving and restoring callee-saved registers efficiently into a register allocation problem. This has the advantage that the register allocator can essentialy do shrink-wrapping on per register basis. Currently, shrink-wrapping pass saves all CSR in the same place which may be suboptimal. Also, improvements to register allocation / coalescing will translate to improvements in shrink-wrapping. In finalizeLowering() we copy all callee-saved registers from a physical register to a virtual one. In all return blocks we copy do the reverse.
1 parent 28731f5 commit f843602

27 files changed

+1034
-187
lines changed

‎.gitlab-ci.yml

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# image should be available on the server
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image:
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name: gitlab.dc1.ventanamicro.com:5005/toolchain/llvm
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entrypoint: [""]
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stages:
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- build
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- test
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- deploy
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# TODO: split this up into several jobs. To do this,
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# need to figure out how to pass files from one job to another.
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build-test-benchmark:
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tags:
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- toolchain
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stage: build
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except:
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variables:
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- $CI_COMMIT_MESSAGE =~ /Merge.+branch\s(.*)\sinto(.*)/
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script:
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- echo "Hello, $GITLAB_USER_LOGIN!"
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- whoami
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- pwd
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# check that we can execute riscv64 with the plugin
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- cp $TEST_RISCV64 .
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- (export USE_QEMU_PLUGIN="1"; export QEMU_CPU="veyron-v2"; ./test-riscv64.elf)
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- ls
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- export BRANCH_NAME=$CI_COMMIT_BRANCH
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# check that needed volumes are mounter correctly
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- export CCACHE_DIR=/mnt/ccache/llvm
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- export ARTIFACTS_DIR=/mnt/artifacts/llvm
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- ls $CCACHE_DIR
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- ls $ARTIFACTS_DIR
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# check that ccache is actually working
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- ccache -s -v
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- export STAGING_DIR=$ARTIFACTS_DIR/staging/$CI_COMMIT_BRANCH
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- rm -rf $STAGING_DIR
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- mkdir -p $STAGING_DIR
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- cp -r /mnt/spec2017 $STAGING_DIR/
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- export SPEC_DIR=$STAGING_DIR/spec2017
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- export BUILD_DIR=$STAGING_DIR/build
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- export INSTALL_DIR=$STAGING_DIR/install
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- make prepare
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- make configure_llvm
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# TODO: run tests
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- make install_llvm
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# run benchmarks with test workload
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- make clean_spec
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- make run_spec_test
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- make check_spec_logs
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# run benchmarks with train workload
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- make clean_spec
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- make run_spec_train
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- make check_spec_logs
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# MKDIR_CP is defined by the docker container
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- $MKDIR_CP -listOfPaths $(ls $SPEC_DIR/cpu2017/benchspec/CPU/*/build/*/*.out) -pathPrefix $STAGING_DIR
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- $MKDIR_CP -listOfPaths $(ls $SPEC_DIR/cpu2017/benchspec/CPU/*/run/*/*.collect) -pathPrefix $STAGING_DIR
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- python3 $PARSE_BENCHMARK_DATA -pathToSpec $SPEC_DIR/cpu2017 -pathToOutput $STAGING_DIR/parsedBenchmarkData.json
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# Baseline has to be first in the -listOfJsonFiles
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#- python3 $REPORT -listOfJsonFiles parsedBenchmarkData.json -dashBoardFile $ARTIFACTS_DIR/dashboard.csv | tee report.txt
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- python3 $REPORT -listOfJsonFiles $ARTIFACTS_DIR/commited/baseline/parsedBenchmarkData.json $STAGING_DIR/parsedBenchmarkData.json -dashBoardFile $ARTIFACTS_DIR/dashboard.csv | tee report.txt
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update-baseline:
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tags:
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- toolchain
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stage: deploy
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script:
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- export ARTIFACTS_DIR=/mnt/artifacts/llvm
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- export BRANCH_NAME=$(python3 $EXTRACT_BRANCH_NAME_FROM_COMMIT_MESSAGE -commitMessage "$CI_COMMIT_MESSAGE")
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- export STAGING_DIR=$ARTIFACTS_DIR/staging/$BRANCH_NAME
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- export INSTALL_DIR=$STAGING_DIR/install
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- make package_llvm
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- mv $STAGING_DIR/ventana-llvm.deb $ARTIFACTS_DIR/latest_build/ventana-llvm.deb
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- rm -rf $STAGING_DIR/build
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- rm -rf $STAGING_DIR/install
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- rm -rf $STAGING_DIR/spec2017
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# GET_THIS_COMMIT_NUM is defined by the docker container
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- python3 $UPDATE_ARTIFACTS -artifactsDir $ARTIFACTS_DIR -branchToCommit=$(python3 $EXTRACT_BRANCH_NAME_FROM_COMMIT_MESSAGE -commitMessage "$CI_COMMIT_MESSAGE") -commitNo=$(python3 $GET_THIS_COMMIT_NUM -commitedDir $ARTIFACTS_DIR/commited)
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only:
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variables:
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- $CI_COMMIT_MESSAGE =~ /Merge.+branch\s(.*)\sinto(.*)/
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‎Makefile

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TOP = $(PWD)
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SHELL := /bin/bash
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prepare:
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rm -rf $(BUILD_DIR)
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rm -rf $(INSTALL_DIR)
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mkdir -p $(BUILD_DIR)
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mkdir -p $(INSTALL_DIR)
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dpkg --extract /mnt/artifacts/gcc/latest_build/ventana-gcc.deb $(INSTALL_DIR)
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configure_llvm:
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cd $(BUILD_DIR); \
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cmake $(TOP)/llvm \
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-G Ninja \
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-DCMAKE_BUILD_TYPE=Release \
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-DLLVM_ENABLE_ASSERTIONS=ON \
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-DCMAKE_C_COMPILER=$(CC) \
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-DCMAKE_CXX_COMPILER=$(CXX) \
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-DCMAKE_CXX_COMPILER_LAUNCHER="ccache" \
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-DCMAKE_CXX_FLAGS="-stdlib=libc++" \
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-DLLVM_USE_LINKER=lld \
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-DBUILD_SHARED_LIBS=ON \
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-DLLVM_TARGETS_TO_BUILD="RISCV" \
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-DLLVM_ENABLE_PROJECTS="clang;lld" \
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-DLLVM_OPTIMIZED_TABLEGEN=ON \
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-DLLVM_PARALLEL_LINK_JOBS=1 \
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-DCMAKE_INSTALL_PREFIX=$(INSTALL_DIR) \
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-DLLVM_BINUTILS_INCDIR=$(INSTALL_DIR)/x86_64-pc-linux-gnu/riscv64-linux-gnu/include \
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-DLLVM_FORCE_VC_REPOSITORY=blah
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configure_llvm_native_riscv64_flang_build:
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rm -rf $(BUILD_DIR)
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mkdir -p $(BUILD_DIR)
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mkdir -p $(INSTALL_DIR)
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cd $(BUILD_DIR); \
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cmake $(TOP)/llvm \
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-G Ninja \
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-DCMAKE_BUILD_TYPE=Release \
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-DLLVM_ENABLE_ASSERTIONS=ON \
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-DLLVM_TARGETS_TO_BUILD="host" \
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-DLLVM_ENABLE_PROJECTS="clang;mlir;flang;openmp" \
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-DCMAKE_C_COMPILER=gcc \
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-DCMAKE_CXX_COMPILER=g++ \
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-DLLVM_PARALLEL_LINK_JOBS=1 \
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-DCMAKE_INSTALL_PREFIX=$(INSTALL_DIR) \
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-DLLVM_ENABLE_RUNTIMES="compiler-rt"
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install_llvm:
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cd $(BUILD_DIR); cmake --build . --target install
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package_llvm:
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mkdir -p $(INSTALL_DIR)/DEBIAN
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echo -e "\
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Package: ventanta-llvm \n\
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Version: 1.0 \n\
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Section: utils \n\
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Priority: optional \n\
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Architecture: all \n\
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Maintainer: Ventana Micro Systems \n\
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Description: LLVM, $(BRANCH_NAME) \n\
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" > $(INSTALL_DIR)/DEBIAN/control
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dpkg-deb --root-owner-group --build $(INSTALL_DIR)
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mv $(STAGING_DIR)/install.deb $(STAGING_DIR)/ventana-llvm.deb
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MCPU=veyron-v1
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SPEC_OPTIMIZE_FLAGS="\
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-mcpu=$(MCPU) \
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--sysroot=$(INSTALL_DIR) \
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-O3 \
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-mllvm -stats \
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"
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SPEC_LD_FLAGS="\
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-fuse-ld=$(INSTALL_DIR)/riscv64-linux-gnu/bin/ld.bfd \
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-static \
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"
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# SPEC_DIR is defined in gitlab-ci.yml
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#
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define runSpecBenchmark
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cd $(SPEC_DIR)/cpu2017; \
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(\
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source shrc; \
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export USE_QEMU_PLUGIN="1"; \
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export QEMU_CPU="$(MCPU)"; \
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runcpu \
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--config=llvm-linux-riscv-ventana.cfg \
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--define label=$(BRANCH_NAME) \
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--define llvm_bin_dir="$(INSTALL_DIR)/bin" \
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--define optimize_flags=$(SPEC_OPTIMIZE_FLAGS) \
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--define ld_flags=$(SPEC_LD_FLAGS) \
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--action=validate \
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--size=$(2) \
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$(1) \
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)
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endef
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run_spec_test:
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$(call runSpecBenchmark,500.perlbench_r,test) & \
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$(call runSpecBenchmark,502.gcc_r,test) & \
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$(call runSpecBenchmark,505.mcf_r,test) & \
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$(call runSpecBenchmark,508.namd_r,test) & \
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$(call runSpecBenchmark,510.parest_r,test) & \
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$(call runSpecBenchmark,511.povray_r,test) & \
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$(call runSpecBenchmark,519.lbm_r,test) & \
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$(call runSpecBenchmark,520.omnetpp_r,test) & \
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$(call runSpecBenchmark,523.xalancbmk_r,test) & \
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$(call runSpecBenchmark,525.x264_r,test) & \
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$(call runSpecBenchmark,526.blender_r,test) & \
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$(call runSpecBenchmark,531.deepsjeng_r,test) & \
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$(call runSpecBenchmark,538.imagick_r,test) & \
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$(call runSpecBenchmark,541.leela_r,test) & \
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$(call runSpecBenchmark,544.nab_r,test) & \
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$(call runSpecBenchmark,557.xz_r,test) & \
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wait
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run_spec_train:
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$(call runSpecBenchmark,500.perlbench_r,train) & \
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$(call runSpecBenchmark,502.gcc_r,train) & \
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$(call runSpecBenchmark,505.mcf_r,train) & \
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$(call runSpecBenchmark,508.namd_r,train) & \
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$(call runSpecBenchmark,510.parest_r,train) & \
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$(call runSpecBenchmark,511.povray_r,train) & \
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$(call runSpecBenchmark,519.lbm_r,train) & \
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$(call runSpecBenchmark,520.omnetpp_r,train) & \
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$(call runSpecBenchmark,523.xalancbmk_r,train) & \
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$(call runSpecBenchmark,525.x264_r,train) & \
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$(call runSpecBenchmark,526.blender_r,train) & \
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$(call runSpecBenchmark,531.deepsjeng_r,train) & \
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$(call runSpecBenchmark,538.imagick_r,train) & \
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$(call runSpecBenchmark,541.leela_r,train) & \
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$(call runSpecBenchmark,544.nab_r,train) & \
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$(call runSpecBenchmark,557.xz_r,train) & \
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wait
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check_spec_logs:
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cd $(SPEC_DIR); \
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python3 spec.py \
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--specCPU2017Path=cpu2017 \
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--checkSpecLogs \
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--benchmarksList="\
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500.perlbench_r,\
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502.gcc_r,\
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505.mcf_r,\
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508.namd_r,\
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510.parest_r,\
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511.povray_r,\
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519.lbm_r,\
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520.omnetpp_r,\
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523.xalancbmk_r,\
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525.x264_r,\
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526.blender_r,\
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531.deepsjeng_r,\
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538.imagick_r,\
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541.leela_r,\
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544.nab_r,\
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557.xz_r\
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"
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clean_spec:
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rm -rf $(SPEC_DIR)/cpu2017/benchspec/C*/*/run
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rm -rf $(SPEC_DIR)/cpu2017/benchspec/C*/*/build
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rm -rf $(SPEC_DIR)/cpu2017/benchspec/C*/*/exe
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rm -rf $(SPEC_DIR)/cpu2017/result/*
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rm -rf $(SPEC_DIR)/cpu2017/tmp/*

‎llvm/include/llvm/CodeGen/ReachingDefAnalysis.h

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@@ -114,8 +114,11 @@ class ReachingDefAnalysis : public MachineFunctionPass {
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private:
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MachineFunction *MF = nullptr;
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const TargetRegisterInfo *TRI = nullptr;
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const TargetInstrInfo *TII = nullptr;
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LoopTraversal::TraversalOrder TraversedMBBOrder;
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unsigned NumRegUnits = 0;
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unsigned NumStackObjects = 0;
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int ObjectIndexBegin = 0;
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/// Instruction that defined each register, relative to the beginning of the
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/// current basic block. When a LiveRegsDefInfo is used to represent a
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/// live-out register, this value is relative to the end of the basic block,
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DenseMap<MachineInstr *, int> InstIds;
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MBBReachingDefsInfo MBBReachingDefs;
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using MBBFrameObjsReachingDefsInfo =
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std::vector<std::vector<std::vector<int>>>;
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MBBFrameObjsReachingDefsInfo MBBFrameObjsReachingDefs;
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142148
/// Default values are 'nothing happened a long time ago'.
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const int ReachingDefDefaultVal = -(1 << 21);

‎llvm/include/llvm/CodeGen/TargetFrameLowering.h

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@@ -24,15 +24,16 @@ namespace llvm {
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class CalleeSavedInfo;
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class MachineFunction;
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class RegScavenger;
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namespace TargetStackID {
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enum Value {
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Default = 0,
31-
SGPRSpill = 1,
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ScalableVector = 2,
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WasmLocal = 3,
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NoAlloc = 255
35-
};
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class ReachingDefAnalysis;
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namespace TargetStackID {
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enum Value {
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Default = 0,
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SGPRSpill = 1,
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ScalableVector = 2,
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WasmLocal = 3,
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NoAlloc = 255
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};
3637
}
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3839
/// Information about stack frame layout on the target. It holds the direction
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/// for noreturn nounwind functions.
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virtual bool enableCalleeSaveSkip(const MachineFunction &MF) const;
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214+
virtual void emitCFIsForCSRsHandledByRA(MachineFunction &MF,
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ReachingDefAnalysis *RDA) const {
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return;
217+
}
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213219
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
214220
/// the function.
215221
virtual void emitPrologue(MachineFunction &MF,

‎llvm/include/llvm/CodeGen/TargetSubtargetInfo.h

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@@ -328,6 +328,8 @@ class TargetSubtargetInfo : public MCSubtargetInfo {
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return false;
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}
330330

331+
virtual bool doCSRSavesInRA() const;
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331333
/// Classify a global function reference. This mainly used to fetch target
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/// special flags for lowering a function address. For example mark a function
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/// call should be plt or pc-related addressing.

‎llvm/include/llvm/DebugInfo/DWARF/DWARFDebugFrame.h

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@@ -74,8 +74,7 @@ class UnwindLocation {
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bool Dereference; /// If true, the resulting location must be dereferenced
7575
/// after the location value is computed.
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// Constructors are private to force people to use the create static
78-
// functions.
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public:
7978
UnwindLocation(Location K)
8079
: Kind(K), RegNum(InvalidRegisterNumber), Offset(0),
8180
AddrSpace(std::nullopt), Dereference(false) {}
@@ -88,7 +87,6 @@ class UnwindLocation {
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: Kind(DWARFExpr), RegNum(InvalidRegisterNumber), Offset(0), Expr(E),
8988
Dereference(Deref) {}
9089

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public:
9290
/// Create a location whose rule is set to Unspecified. This means the
9391
/// register value might be in the same register but it wasn't specified in
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/// the unwind opcodes.
@@ -135,6 +133,7 @@ class UnwindLocation {
135133
assert(Kind == RegPlusOffset && AddrSpace);
136134
return *AddrSpace;
137135
}
136+
bool getDeref() const { return Dereference; }
138137
int32_t getConstant() const { return Offset; }
139138
/// Some opcodes will modify the CFA location's register only, so we need
140139
/// to be able to modify the CFA register when evaluating DWARF Call Frame
@@ -148,6 +147,11 @@ class UnwindLocation {
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/// the constant value (DW_CFA_GNU_window_save which is also known as
149148
// DW_CFA_AARCH64_negate_ra_state).
150149
void setConstant(int32_t Value) { Offset = Value; }
150+
void setDeref(bool NewDeref) { Dereference = NewDeref; }
151+
void setKind(Location NewKind) { Kind = NewKind; }
152+
bool isRegister() const {
153+
return ((Kind == RegPlusOffset) && !Dereference && (Offset == 0));
154+
}
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152156
std::optional<DWARFExpression> getDWARFExpressionBytes() const {
153157
return Expr;

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