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guy-davidguy-david
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Manually fixed tests
1 parent f0aef46 commit fbcb84e

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‎llvm/test/CodeGen/Hexagon/swp-conv3x3-nested.ll

+1-2
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; RUN: llc -mtriple=hexagon < %s -pipeliner-experimental-cg=true | FileCheck %s
22

33
; This version of the conv3x3 test has both loops. This test checks that the
4-
; inner loop has 14 packets.
4+
; inner loop has 13 packets.
55

66
; CHECK: loop0(.LBB0_[[LOOP:.]],
77
; CHECK: .LBB0_[[LOOP]]:
@@ -17,7 +17,6 @@
1717
; CHECK: }
1818
; CHECK: }
1919
; CHECK: }
20-
; CHECK: }
2120
; CHECK-NOT: }
2221
; CHECK: }{{[ \t]*}}:endloop0
2322

‎llvm/test/CodeGen/Hexagon/swp-matmul-bitext.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
; From coremark. Test that we pipeline the matrix multiplication bitextract
44
; function. The pipelined code should have two packets.
55

6-
; CHECK: loop0(.LBB0_[[LOOP:.]],
6+
; CHECK: loop0(.LBB0_[[LOOP:[0-9]+]],
77
; CHECK: .LBB0_[[LOOP]]:
88
; CHECK: [[REG0:(r[0-9]+)]] = mpyi([[REG1:(r[0-9]+)]],[[REG2:(r[0-9]+)]])
99
; CHECK: += mpyi

‎llvm/test/CodeGen/Hexagon/swp-stages4.ll

+2-5
Original file line numberDiff line numberDiff line change
@@ -3,11 +3,8 @@
33
; Test that we rename registers correctly for multiple stages when there is a
44
; Phi and depends upon another Phi.
55

6-
; CHECK: = and
7-
; CHECK: = and
8-
; CHECK: r[[REGA:[0-9]+]] = memub(r{{[0-9]+}}+#1)
9-
; CHECK: = and
10-
; CHECK: r[[REG0:[0-9]+]] = and(r[[REG1:[0-9]+]],#255)
6+
; CHECK: jump
7+
; CHECK-NEXT: r[[REG0:[0-9]+]] = and(r[[REG1:[0-9]+]],#255)
118
; CHECK-NOT: r[[REG0]] = and(r[[REG1]],#255)
129
; CHECK: loop0(.LBB0_[[LOOP:.]],
1310
; CHECK: .LBB0_[[LOOP]]:

‎llvm/test/CodeGen/Hexagon/tinycore.ll

+8-3
Original file line numberDiff line numberDiff line change
@@ -8,10 +8,15 @@
88
; CHECK: .LBB0_[[LOOP]]:
99
; CHECK: {
1010
; CHECK-NEXT: mpy
11-
; CHECK-NEXT: combine
12-
; CHECK-NEXT: memw
13-
; CHECK-NEXT: }
11+
; CHECK-NOT: memw
12+
; CHECK: }
13+
; CHECK: {
14+
; CHECK: memw
15+
; CHECK-NOT: memw
16+
; CHECK: }
17+
; CHECK: {
1418
; CHECK: memw
19+
; CHECK-NOT: memw
1520
; CHECK: } :endloop0
1621

1722
; Test the loop contains a single packet with 4 instructions.

‎llvm/test/CodeGen/PowerPC/2013-07-01-PHIElimBug.mir

+1-2
Original file line numberDiff line numberDiff line change
@@ -80,10 +80,9 @@ body: |
8080
# CHECK-NEXT: %15:g8rc = COPY killed %6
8181
# CHECK: bb.3:
8282
# CHECK: %10:g8rc = COPY killed %15
83-
# CHECK-NEXT: %9:g8rc = COPY killed %14
83+
# CHECK-NEXT: %16:g8rc_and_g8rc_nox0 = COPY killed %14
8484
# CHECK-NEXT: %14:g8rc = COPY killed %10
8585
# CHECK-NEXT: %15:g8rc = IMPLICIT_DEF
86-
# CHECK-NEXT: %16:g8rc_and_g8rc_nox0 = COPY killed %9
8786
# CHECK-NEXT: BCC 68, %7, %bb.3
8887
# CHECK-NEXT: B %bb.4
8988
# CHECK: bb.4:

‎llvm/test/CodeGen/PowerPC/phi-eliminate.mir

+3-6
Original file line numberDiff line numberDiff line change
@@ -195,12 +195,9 @@ body: |
195195
; CHECK: bb.4:
196196
; CHECK: successors: %bb.5(0x80000000)
197197
; CHECK: %44:g8rc_and_g8rc_nox0 = COPY killed %59
198-
; CHECK: %43:gprc = COPY killed %57
199-
; CHECK: %41:gprc = COPY killed %60
200-
; CHECK: %39:g8rc = COPY killed %44
201-
; CHECK: %61:gprc = COPY killed %41
202-
; CHECK: %62:g8rc_and_g8rc_nox0 = COPY killed %39
203-
; CHECK: %63:gprc = COPY killed %43
198+
; CHECK: %63:gprc = COPY killed %57
199+
; CHECK: %61:gprc = COPY killed %60
200+
; CHECK: %62:g8rc_and_g8rc_nox0 = COPY killed %44
204201
205202
; CHECK: bb.5:
206203
; CHECK: successors: %bb.6(0x80000000)

‎llvm/test/CodeGen/PowerPC/ppcf128-freeze.mir

+15-15
Original file line numberDiff line numberDiff line change
@@ -1,21 +1,10 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
12
# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -start-after=codegenprepare \
23
# RUN: -o - %s -verify-machineinstrs | FileCheck %s
34

45
--- |
56
define ppc_fp128 @freeze_select(ppc_fp128 %a, ppc_fp128 %b) {
6-
%sel.frozen = freeze ppc_fp128 %a
7-
%cmp = fcmp one ppc_fp128 %sel.frozen, 0xM00000000000000000000000000000000
8-
br i1 %cmp, label %select.end, label %select.false
9-
10-
select.false: ; preds = %0
11-
br label %select.end
12-
13-
select.end: ; preds = %0, %select.false
14-
%sel = phi ppc_fp128 [ %a, %0 ], [ %b, %select.false ]
15-
ret ppc_fp128 %sel
16-
}
17-
18-
; CHECK-LABEL: freeze_select
7+
; CHECK-LABEL: freeze_select:
198
; CHECK: # %bb.0:
209
; CHECK-NEXT: xxlxor 0, 0, 0
2110
; CHECK-NEXT: fcmpu 1, 2, 2
@@ -28,8 +17,19 @@
2817
; CHECK-NEXT: # %bb.1:
2918
; CHECK-NEXT: crnor 20, 7, 2
3019
; CHECK-NEXT: bclr 12, 20, 0
31-
; CHECK-NEXT: # %bb.2: # %select.false
32-
; CHECK-NEXT: fmr 1, 3
20+
; CHECK-NEXT: # %bb.2: # %select.false
3321
; CHECK-NEXT: fmr 2, 4
22+
; CHECK-NEXT: fmr 1, 3
3423
; CHECK-NEXT: blr
24+
%sel.frozen = freeze ppc_fp128 %a
25+
%cmp = fcmp one ppc_fp128 %sel.frozen, 0xM00000000000000000000000000000000
26+
br i1 %cmp, label %select.end, label %select.false
27+
28+
select.false: ; preds = %0
29+
br label %select.end
30+
31+
select.end: ; preds = %0, %select.false
32+
%sel = phi ppc_fp128 [ %a, %0 ], [ %b, %select.false ]
33+
ret ppc_fp128 %sel
34+
}
3535
...

‎llvm/test/CodeGen/PowerPC/pr116071.ll

+18-7
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,26 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
12
; RUN: llc -disable-ppc-vsx-fma-mutation=false -mcpu=pwr10 -verify-machineinstrs \
2-
; RUN: -ppc-asm-full-reg-names -mtriple powerpc64-ibm-aix7.2.0.0 < %s | FileCheck %s
3+
; RUN: -ppc-asm-full-reg-names -mtriple powerpc64-ibm-aix7.2.0.0 < %s | FileCheck %s
34

45
target datalayout = "E-m:a-Fi64-i64:64-n32:64-S128-v256:256:256-v512:512:512"
56

67
define void @initial(<2 x double> %0){
8+
; CHECK-LABEL: initial:
9+
; CHECK: # %bb.0: # %entry
10+
; CHECK-NEXT: xxlxor vs0, vs0, vs0
11+
; CHECK-NEXT: xxlxor f2, f2, f2
12+
; CHECK-NEXT: xxlxor f4, f4, f4
13+
; CHECK-NEXT: xxlxor f3, f3, f3
14+
; CHECK-NEXT: xvmuldp vs1, vs34, vs0
15+
; CHECK-NEXT: .align 5
16+
; CHECK-NEXT: L..BB0_1: # %for.cond251.preheader.lr.ph
17+
; CHECK-NEXT: #
18+
; CHECK-NEXT: fmr f5, f3
19+
; CHECK-NEXT: xsadddp f3, f3, f4
20+
; CHECK-NEXT: fmr f4, f5
21+
; CHECK-NEXT: xxmrghd vs3, vs3, vs2
22+
; CHECK-NEXT: xvmaddmdp vs3, vs0, vs1
23+
; CHECK-NEXT: b L..BB0_1
724
entry:
825
%1 = fmul <2 x double> %0, zeroinitializer
926
br label %for.cond251.preheader.lr.ph
@@ -18,9 +35,3 @@ for.cond251.preheader.lr.ph: ; preds = %for.cond251.prehead
1835
%7 = extractelement <2 x double> %6, i64 0
1936
br label %for.cond251.preheader.lr.ph
2037
}
21-
22-
; CHECK: xsadddp f4, f3, f4
23-
; CHECK-NEXT: xxmrghd vs5, vs4, vs2
24-
; CHECK-NEXT: fmr f4, f3
25-
; CHECK-NEXT: xvmaddmdp vs5, vs0, vs1
26-
; CHECK-NEXT: fmr f3, f5

‎llvm/test/CodeGen/SystemZ/swifterror.ll

+2-2
Original file line numberDiff line numberDiff line change
@@ -162,8 +162,8 @@ define float @foo_loop(ptr swifterror %error_ptr_ref, i32 %cc, float %cc2) {
162162
; CHECK-O0: je
163163
; CHECK-O0: lghi %r2, 16
164164
; CHECK-O0: brasl %r14, malloc
165-
; CHECK-O0: lgr %r[[REG1:[0-9]+]], %r2
166-
; CHECK-O0: mvi 8(%r[[REG1]]), 1
165+
; CHECK-O0: lgr %r{{[0-9]+}}, %r2
166+
; CHECK-O0: mvi 8(%r2), 1
167167
; CHECK-O0: jnh
168168
; reload from stack
169169
; CHECK-O0: lg %r9, [[OFFS:[0-9]+]](%r15)

‎llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@ zero:
6060
; CHECK: JMP_1 %bb.4
6161
; CHECK: bb.4
6262
; CHECK: bb.5
63-
; CHECK: %3:gr64 = COPY %10
63+
; CHECK: %20:gr64 = COPY %10
6464
; CHECK: %4:gr64 = COPY killed %10
6565
; CHECK: %4:gr64 = nuw ADD64ri32 %4, 8, implicit-def dead $eflags
6666
; CHECK: TEST64rr killed %1, %1, implicit-def $eflags

‎llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir

+3-4
Original file line numberDiff line numberDiff line change
@@ -70,8 +70,7 @@ frameInfo:
7070
machineFunctionInfo: {}
7171
body: |
7272
; CHECK-LABEL: bb.0:
73-
; CHECK: renamable $ebp = COPY $edi
74-
; CHECK: MOV32mr %stack.1, 1, $noreg, 0, $noreg, killed renamable $ebp
73+
; CHECK: MOV32mr %stack.[[SLOT:.+]], 1, $noreg, 0, $noreg, $edi
7574
bb.0:
7675
successors: %bb.2(0x50000000), %bb.1(0x30000000)
7776
liveins: $edi, $esi
@@ -142,8 +141,8 @@ body: |
142141
%64:gr32 = PHI %24, %bb.0, %44, %bb.1, debug-location !18
143142
144143
DBG_INSTR_REF !14, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0), debug-location !12
145-
; CHECK: DBG_PHI %stack.1, 1, 32
146-
; CHECK: renamable $eax = MOV32rm %stack.1,
144+
; CHECK: DBG_PHI %stack.[[SLOT]], 1, 32
145+
; CHECK: renamable $eax = MOV32rm %stack.[[SLOT]],
147146
; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
148147
$eax = COPY killed %0, debug-location !19
149148
RET 0, killed $eax, debug-location !19

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