[AVX-512] Propagating lowest bit to all bits in u64 lane should use `sra(sll(x, 63), 63)` instead of `neg(and(x, 1))`

[Validark]

Zig Godbolt LLVM Godbolt

export fn foo(vec: @Vector(8, u64)) @Vector(8, u64) {
    return -%((vec << @splat(63)) >> @splat(63));
}

Gives:

.LCPI0_0:
        .quad   1
foo:
        vpandq  zmm0, zmm0, qword ptr [rip + .LCPI0_0]{1to8}
        vpxor   xmm1, xmm1, xmm1
        vpsubq  zmm0, zmm1, zmm0
        ret

Should be:

foo:
        vpsllq  zmm0, zmm0, 63
        vpsraq  zmm0, zmm0, 63
        ret

[Validark]

Btw, directly asking for this optimization like the following block of code still gets lowered by LLVM to the same sequence. So, the good news is, all of the ways I would think to write this code get lowered to the same thing. All someone needs to do is go change the sequence it prefers, or optimize the final sequence to the optimization I want to see. And thank you to anyone who fixes this!

export fn foo(vec: @Vector(8, u64)) @Vector(8, u64) {
    return @bitCast(@as(@Vector(8, i64), @bitCast(vec << @splat(63))) >> @splat(63));
}

[llvmbot]

@llvm/issue-subscribers-backend-x86

Author: Niles Salter (Validark)

[Zig Godbolt](https://zig.godbo.lt/#g:!((g:!((g:!((h:codeEditor,i:(filename:'1',fontScale:13,fontUsePx:'0',j:1,lang:zig,selection:(endColumn:1,endLineNumber:13,positionColumn:1,positionLineNumber:13,selectionStartColumn:1,selectionStartLineNumber:13,startColumn:1,startLineNumber:13),source:'export+fn+foo(vec:+@Vector(8,+u64))+@Vector(8,+u64)+%7B%0A++++return+-%25((vec+%3C%3C+@splat(63))+%3E%3E+@splat(63))%3B%0A%7D%0A%0Aexport+fn+bar(vec:+@Vector(8,+u64))+@Vector(8,+u64)+%7B%0A++++return+asm+(%0A++++++++%5C%5C+vpsllq+$63,+%25%5Bvec%5D,+%25%5Bresult%5D%0A++++++++%5C%5C+vpsraq+$63,+%25%5Bresult%5D,+%25%5Bresult%5D%0A++++++++:+%5Bresult%5D+%22%3Dx%22+(-%3E+@Vector(8,+u64)),%0A++++++++:+%5Bvec%5D+%22x%22+(vec),%0A++++)%3B%0A%7D%0A'),l:'5',n:'0',o:'Zig+source+%231',t:'0')),k:51.313288405045796,l:'4',n:'0',o:'',s:0,t:'0'),(g:!((h:compiler,i:(compiler:ztrunk,filters:(b:'0',binary:'1',binaryObject:'1',commentOnly:'0',debugCalls:'1',demangle:'0',directives:'0',execute:'1',intel:'0',libraryCode:'0',trim:'1',verboseDemangling:'0'),flagsViewOpen:'1',fontScale:13,fontUsePx:'0',j:3,lang:zig,libs:!(),options:'-O+ReleaseFast+-target+x86_64-linux+-mcpu%3Dznver5',overrides:!(),selection:(endColumn:1,endLineNumber:1,positionColumn:1,positionLineNumber:1,selectionStartColumn:1,selectionStartLineNumber:1,startColumn:1,startLineNumber:1),source:1),l:'5',n:'0',o:'+zig+trunk+(Editor+%231)',t:'0')),header:(),k:48.68671159495422,l:'4',m:100,n:'0',o:'',s:0,t:'0')),l:'2',n:'0',o:'',t:'0')),version:4) [LLVM Godbolt](https://llvm.godbolt.org/#g:!((g:!((g:!((h:codeEditor,i:(filename:'1',fontScale:14,fontUsePx:'0',j:1,lang:llvm,selection:(endColumn:1,endLineNumber:13,positionColumn:1,positionLineNumber:13,selectionStartColumn:1,selectionStartLineNumber:13,startColumn:1,startLineNumber:13),source:'define+dso_local+range(i64+-1,+1)+%3C8+x+i64%3E+@foo(%3C8+x+i64%3E+%250)+local_unnamed_addr+%7B%0AEntry:%0A++%251+%3D+and+%3C8+x+i64%3E+%250,+splat+(i64+1)%0A++%252+%3D+sub+nsw+%3C8+x+i64%3E+zeroinitializer,+%251%0A++ret+%3C8+x+i64%3E+%252%0A%7D%0A%0Adefine+dso_local+%3C8+x+i64%3E+@bar(%3C8+x+i64%3E+%250)+local_unnamed_addr+%7B%0AEntry:%0A++%251+%3D+tail+call+%3C8+x+i64%3E+asm+%22+vpsllq+$$63,+$%7B1%7D,+$%7B0%7D%5C0A+vpsraq+$$63,+$%7B0%7D,+$%7B0%7D%22,+%22%3Dx,x,~%7Bdirflag%7D,~%7Bfpsr%7D,~%7Bflags%7D%22(%3C8+x+i64%3E+%250)+%232%0A++ret+%3C8+x+i64%3E+%251%0A%7D%0A'),l:'5',n:'0',o:'LLVM+IR+source+%231',t:'0')),k:49.178082191780824,l:'4',n:'0',o:'',s:0,t:'0'),(g:!((h:compiler,i:(compiler:irclangtrunk,filters:(b:'0',binary:'1',binaryObject:'1',commentOnly:'0',debugCalls:'1',demangle:'0',directives:'0',execute:'1',intel:'0',libraryCode:'0',trim:'1',verboseDemangling:'0'),flagsViewOpen:'1',fontScale:14,fontUsePx:'0',j:1,lang:llvm,libs:!(),options:'-O3+-march%3Dznver5',overrides:!(),selection:(endColumn:1,endLineNumber:1,positionColumn:1,positionLineNumber:1,selectionStartColumn:1,selectionStartLineNumber:1,startColumn:1,startLineNumber:1),source:1),l:'5',n:'0',o:'+clang+(trunk)+(Editor+%231)',t:'0')),k:50.82191780821918,l:'4',m:100,n:'0',o:'',s:0,t:'0')),l:'2',n:'0',o:'',t:'0')),version:4) ```zig export fn foo(vec: @Vector(8, u64)) @Vector(8, u64) { return -%((vec << @splat(63)) >> @splat(63)); } ```

Gives:

.LCPI0_0:
        .quad   1
foo:
        vpandq  zmm0, zmm0, qword ptr [rip + .LCPI0_0]{1to8}
        vpxor   xmm1, xmm1, xmm1
        vpsubq  zmm0, zmm1, zmm0
        ret

Should be:

foo:
        vpsllq  zmm0, zmm0, 63
        vpsraq  zmm0, zmm0, 63
        ret

[dzaima]

The difference instruction-count-wise is just the initialization of constant vectors, which'd be factored out in usage within a loop (assuming not hitting register pressure, I guess).

And shifts have less throughput as per uops.info data (for zmm, 1/cycle for both shift kinds, whereas vpandq and vpsubq have throughput of 2/cycle; for ymm, 2/cycle for shifts, vs 3/cycle (Intel) & 4/cycle (Zen 4) for and/sub).

[Validark]

The difference instruction-count-wise is just the initialization of constant vectors, which'd be factored out in usage within a loop (assuming not hitting register pressure, I guess).

And shifts have less throughput as per uops.info data (for zmm, 1/cycle for both shift kinds, whereas vpandq and vpsubq have throughput of 2/cycle; for ymm, 2/cycle for shifts, vs 3/cycle (Intel) & 4/cycle (Zen 4) for and/sub).

Hmm, yeah this is a more complex tradeoff than I thought. I didn't realize the throughput would be lower for shifts. I just assumed those would go on the same ALUs as the other basic operations but I guess not.