Description
| Bugzilla Link | 44044 |
| Version | trunk |
| OS | All |
| Reporter | LLVM Bugzilla Contributor |
| CC | @rotateright |
Extended Description
A number of comparisons involving bit tests are converted into shifts by InstCombine and DAGCombine. However, shifts are expensive for most 8 and 16 bit targets with comparatively cheaper selects.
It is desirable that selects are emitted instead of shifts for these targets. The following cases were identified in TargetLowering and DAGCombine and were fixed by:
https://reviews.llvm.org/D69116
https://reviews.llvm.org/D69120
https://reviews.llvm.org/D69326
https://reviews.llvm.org/D70042
Cases in InstCombine remain to be fixed. In llvm-dev it has been suggested that these cases should be fixed by reversing the current canonicalisation. I am showing them in this and following reports:
REPORTED CASE:
Source code:
int testShiftAnd_1more( int x ) // (InstCombineCasts::transformZExtICmp)
{
return x<0 ;
}
IR code:
define i16 @testShiftAnd_1more(i16 %x) {
entry:
%x.lobit = lshr i16 %x, 15
ret i16 %x.lobit
}
MSP430 Target code:
testShiftAnd_1more:
swpb r12
mov.b r12, r12
clrc
rrc r12
rra r12
rra r12
rra r12
rra r12
rra r12
rra r12
ret
AVR Target code:
testShiftAnd_1more:
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
lsr r25
ror r24
ret
EXPECTED RESULT:
Source code:
int testShiftAnd_1more( int x ) // (InstCombineCasts::transformZExtICmp)
{
return x<0 ;
}
Expected IR code:
define i16 @testShiftAnd_1more(i16 %x) {
entry:
%cmp = icmp slt i16 %x, 0
%conv = zext i1 %cmp to i16
ret i16 %conv
}
Expected MSP430 Target code:
testShiftAnd_1more:
mov r12, r13
mov llvm/llvm-project#373, r12
tst r13
jl .LBB6_2
clr r12
.LBB6_2:
ret
Expected AVR Target code:
testShiftAnd_1more:
ldi r18, 1
tst r25
brmi LBB6_2
ldi r18, 0
LBB6_2:
mov r24, r18
clr r25
ret