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‎LICENSE_3RD_PARTY.md

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# Open Source License Acknowledgements and Third-Party Copyrights
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TreeCore CPU utilizes third party software from various sources. Portions of this software are copyrighted by their respective owners as indicated in the copyright notices below.
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The following acknowledgements pertain to this software license.
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## Main components used by TreeCore CPU
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These components are installed via composer or via npm. You can check all the dependencies using the instructions from the section Libraries dynamically referenced via Composer and Libraries dynamically referenced via npm.
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### verilator
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* maintainer: [verilator](https://github.com/verilator)
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* License: [LGPL-3.0](https://github.com/verilator/verilator/blob/master/LICENSE)
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* repo: https://github.com/verilator/verilator
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### mill
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* maintainer: [com-lihaoyi](https://github.com/com-lihaoyi)
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* License: [MIT](https://github.com/com-lihaoyi/mill/blob/main/LICENSE)
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* repo: https://github.com/com-lihaoyi/mill
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### riscv-test
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* maintainer: [NJU-ProjectN](https://github.com/NJU-ProjectN)
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* License: [custom](https://github.com/NJU-ProjectN/riscv-tests/blob/master/LICENSE)
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* repo: https://github.com/NJU-ProjectN/riscv-tests
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### difftest
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* maintainer: [oscpu](https://gitee.com/oscpu)
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* License: [MulanPSL-2.0](https://gitee.com/oscpu/difftest/blob/master/LICENSE)
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* repo: https://gitee.com/oscpu/difftest
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### NEMU
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* maintainer: [oscpu](https://gitee.com/oscpu)
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* License: [MulanPSL-2.0](https://gitee.com/oscpu/difftest/blob/master/LICENSE)
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* repo: https://gitee.com/oscpu/NEMU
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### DRAMsim3
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* maintainer: [OpenXiangShan](https://github.com/OpenXiangShan)
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* License: [MIT](https://github.com/OpenXiangShan/DRAMsim3/blob/co-simulation/LICENSE)
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* repo: https://github.com/OpenXiangShan/DRAMsim3
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### ysyxSoC
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* maintainer: [oscpu](https://github.com/OSCPU)
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* License: [custom](https://github.com/OSCPU/ysyxSoC/blob/master/LICENSE.Berkeley)
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* repo: https://github.com/OSCPU/ysyxSoC
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## Libraries modified for TreeCore CPU
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These libraries derive from [NJU-ProjectN](https://github.com/NJU-ProjectN) and are modified specifically for TreeCore CPU.
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### abstract-machine
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* maintainer: [maksyuki](https://github.com/maksyuki)
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* License: [GPL-3.0](https://github.com/maksyuki/ysyx-software-file/blob/master/LICENSE)
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* repo: https://github.com/maksyuki/ysyx-software-file/tree/master/abstract-machine
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### am-kernels
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* maintainer: [maksyuki](https://github.com/maksyuki)
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* License: [GPL-3.0](https://github.com/maksyuki/ysyx-software-file/blob/master/LICENSE)
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* repo: https://github.com/maksyuki/ysyx-software-file/tree/master/am-kernels

‎README.md

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## Update
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## License
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All of the TreeCore codes are release under the [GPL-3.0 License](LICENSE).
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TreeCore CPU's codes are release under the [GPL-3.0 License](LICENSE) and compliance with other open source agreements. You can find all 3rd party libraries licenses in [LICENSE_3RD_PARTY.md](LICENSE_3RD_PARTY).
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## Acknowledgement
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1. [oscpu-framework](https://github.com/OSCPU/oscpu-framework)

‎rtl/scripts/install.sh

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‎rtl/scripts/record.sh

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#!/bin/bash
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‎rtl/tc_l1/hello/Makefile

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comp:
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verilator -Wall --cc --exe --build hello.cpp hello.v -o emu -Mdir build
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run:
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./build/emu
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.PHONY:
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comp run

‎rtl/tc_l1/hello/hello.cpp

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#include "Vhello.h"
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#include "verilated.h"
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int main(int argc, char **argv, char **env)
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{
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VerilatedContext *contextp = new VerilatedContext;
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contextp->commandArgs(argc, argv);
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Vhello *top = new Vhello{contextp};
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while (!contextp->gotFinish())
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{
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top->eval();
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}
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delete top;
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delete contextp;
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return 0;
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}

‎rtl/tc_l1/hello/hello.v

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module hello;
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initial begin
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$display("Hello World");
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$finish;
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end
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endmodule

‎rtl/tc_l1/switch/Makefile

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comp:
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verilator -Wall --cc --exe --build top.cpp top.v -o emu -Mdir build
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run:
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./build/emu
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.PHONY:
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comp run

‎rtl/tc_l1/switch/top.cpp

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#include <stdio.h>
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#include <stdlib.h>
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#include <assert.h>
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#include "Vtop.h"
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#include "verilated.h"
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int main(int argc, char **argv, char **env)
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{
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VerilatedContext *contextp = new VerilatedContext;
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contextp->commandArgs(argc, argv);
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Vtop *top = new Vtop{contextp};
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while (!contextp->gotFinish())
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{
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int a = rand() & 1;
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int b = rand() & 1;
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top->a = a;
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top->b = b;
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top->eval();
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printf("a = %d, b = %d, f = %d\n", a, b, top->f);
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assert(top->f == a ^ b);
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}
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delete top;
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delete contextp;
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return 0;
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}

‎rtl/tc_l1/switch/top.v

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module top(
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input a,
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input b,
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output f
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);
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assign f = a ^ b;
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endmodule

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