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Commit e1e5773

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feat: modify some vars's name
1 parent 5548122 commit e1e5773

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2 files changed

+6
-6
lines changed

2 files changed

+6
-6
lines changed

rtl/tc_l2/src/main/scala/core/if/BTB.scala

+3-3
Original file line numberDiff line numberDiff line change
@@ -40,9 +40,9 @@ class BTB extends Module {
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}
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4242
// signals about BTB lookup
43-
val lookupIdx = io.lookupPc(ConstVal.BTBIdxLen - 1, 0)
44-
val lookupPcSel = io.lookupPc
45-
val btbHit = valids(lookupIdx) && lines(lookupIdx).pc === lookupPcSel
43+
protected val lookupIdx = io.lookupPc(ConstVal.BTBIdxLen - 1, 0)
44+
protected val lookupPcSel = io.lookupPc
45+
protected val btbHit = valids(lookupIdx) && lines(lookupIdx).pc === lookupPcSel
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4747
// BTB lookup
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io.lookupBranch := btbHit

rtl/tc_l2/src/main/scala/core/if/GHR.scala

+3-3
Original file line numberDiff line numberDiff line change
@@ -12,11 +12,11 @@ class GHR extends Module {
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val idx = Output(UInt(ConstVal.GHRLen.W))
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})
1414

15-
protected val ghr = Reg(UInt(ConstVal.GHRLen.W))
15+
protected val shiftReg = Reg(UInt(ConstVal.GHRLen.W))
1616

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when(io.branch) {
18-
ghr := Cat(ghr(ConstVal.GHRLen - 2, 0), io.taken)
18+
shiftReg := Cat(shiftReg(ConstVal.GHRLen - 2, 0), io.taken)
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}
2020

21-
io.idx := ghr
21+
io.idx := shiftReg
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}

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