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Copy pathnano_jpeg.optlite.64.asm
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nano_jpeg.optlite.64.asm
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# write_s RegStats: 0/ 3 0/ 3
# write_c RegStats: 0/ 0 0/ 7
# print_s_ln RegStats: 0/ 0 0/ 3
# abort RegStats: 0/ 0 0/ 2
# malloc RegStats: 3/ 0 1/18
# free RegStats: 0/ 0 0/ 1
# mymemset RegStats: 0/ 4 0/ 2
# mymemcpy RegStats: 0/ 4 0/ 2
# njGetWidth RegStats: 0/ 0 0/ 1
# njGetHeight RegStats: 0/ 0 0/ 1
# njIsColor RegStats: 0/ 0 0/ 1
# njGetImage RegStats: 0/ 0 0/ 3
# njGetImageSize RegStats: 0/ 0 0/ 7
# njClip RegStats: 0/ 1 0/ 1
# njRowIDCT RegStats: 0/ 8 0/55
# njColIDCT RegStats: 9/ 2 1/93
# __static_1_njShowBits RegStats: 0/ 2 0/41
# njSkipBits RegStats: 1/ 0 0/ 4
# njGetBits RegStats: 0/ 0 2/ 0
# njByteAlign RegStats: 0/ 0 0/ 2
# __static_2_njSkip RegStats: 0/ 0 0/ 8
# njDecode16 RegStats: 0/ 0 0/ 8
# __static_3_njDecodeLength RegStats: 0/ 0 0/ 6
# njSkipMarker RegStats: 0/ 0 0/ 1
# njDecodeSOF RegStats: 4/ 1 0/109
# njDecodeDHT RegStats: 5/ 3 0/22
# njDecodeDQT RegStats: 0/ 2 0/14
# njDecodeDRI RegStats: 0/ 0 0/ 6
# njGetVLC RegStats: 4/ 0 0/10
# njDecodeBlock RegStats: 3/ 1 1/51
# njDecodeScan RegStats: 8/ 0 0/65
# njUpsampleH RegStats: 7/ 0 0/135
# njUpsampleV RegStats: 9/ 0 1/129
# njConvert RegStats: 11/ 0 3/56
# njInit RegStats: 0/ 0 0/ 1
# njDone RegStats: 1/ 0 0/10
# njDecode RegStats: 0/ 1 2/24
# write_str RegStats: 0/ 3 0/ 3
# write_dec RegStats: 0/ 3 0/ 5
# main RegStats: 3/ 0 3/30
.mem __static_2__malloc_end 8 RW
.data 8 "\x00"
.mem __static_1__malloc_start 8 RW
.data 8 "\x00"
.mem __static_4_counts 1 RW
.data 16 "\x00"
.mem nj 8 RW
.data 525032 "\x00"
.mem njZZ 1 RW
.data 1 "\x00\x01\x08\x10\x09\x02\x03\n\x11\x18 \x19\x12\x0b\x04\x05\x0c\x13\x1a!(0)\"\x1b\x14\x0d\x06\x07\x0e\x15\x1c#*1892+$\x1d\x16\x0f\x17\x1e%,3:;4-&\x1f'.5<=6/7>?"
.mem string_const_1 4 RO
.data 1 "Usage: nanojpeg <input.jpg> <output.ppm>\x00"
.mem string_const_2 4 RO
.data 1 "Error opening the input file.\x00"
.mem string_const_3 4 RO
.data 1 "Error decoding the input file.\x00"
.mem string_const_4 4 RO
.data 1 "Error opening the output file.\x00"
.mem string_const_5 4 RO
.data 1 "P6\n\x00"
.mem string_const_6 4 RO
.data 1 "P5\n\x00"
.mem string_const_7 4 RO
.data 1 " \x00"
.mem string_const_8 4 RO
.data 1 "\n\x00"
.mem string_const_9 4 RO
.data 1 "255\n\x00"
.fun exit BUILTIN [] = [S32]
.fun xbrk BUILTIN [A64] = [A64]
.fun open BUILTIN [S32] = [A64 S32 S32]
.fun close BUILTIN [S32] = [S32]
.fun write BUILTIN [S64] = [S32 A64 U64]
.fun read BUILTIN [S64] = [S32 A64 U64]
.fun lseek BUILTIN [S64] = [S32 S64 S32]
.fun kill BUILTIN [S32] = [S32 S32]
.fun getpid BUILTIN [S32] = []
.fun write_s NORMAL [S64] = [S32 A64]
.reg S8 [%S8_3]
.reg S32 [%S32_4 fd]
.reg S64 [%out]
.reg U64 [len]
.reg A64 [s]
.bbl %start # edge_out[while_1_cond] live_out[fd len s]
poparg fd
poparg s
mov len 0
bra while_1_cond
.bbl while_1 # edge_out[while_1_cond] live_out[fd len s]
add len len 1
.bbl while_1_cond # edge_out[while_1 while_1_exit] live_out[fd len s]
ld %S8_3 s len
conv %S32_4 %S8_3
bne %S32_4 0 while_1
.bbl while_1_exit
pusharg len
pusharg s
pusharg fd
bsr write
poparg %out
pusharg %out
ret
.fun write_c NORMAL [S64] = [S32 U8]
.reg S8 [%S8_1]
.reg S32 [%S32_6 fd]
.reg S64 [%S64_4 %out]
.reg U8 [c]
.reg A64 [%A64_3]
.stk buffer 1 16
.bbl %start
poparg fd
poparg c
conv %S8_1 c
st.stk buffer 0 %S8_1
lea.stk %A64_3 buffer 0
pusharg 1:U64
pusharg %A64_3
pusharg fd
bsr write
poparg %S64_4
conv %S32_6 %S64_4
conv %out %S32_6
pusharg %out
ret
.fun print_s_ln NORMAL [] = [A64]
.reg S64 [%S64_1 %S64_3]
.reg A64 [s]
.bbl %start
poparg s
pusharg s
pusharg 1:S32
bsr write_s
poparg %S64_1
pusharg 10:U8
pusharg 1:S32
bsr write_c
poparg %S64_3
ret
.fun abort NORMAL [] = []
.reg S32 [%S32_1 %S32_2]
.bbl %start
bsr getpid
poparg %S32_1
pusharg 3:S32
pusharg %S32_1
bsr kill
poparg %S32_2
pusharg 1:S32
bsr exit
ret
.fun malloc NORMAL [A64] = [U64]
.reg U64 [%U64_10 %U64_11 %U64_18 %U64_19 %U64_20 increment page_size rounded_size size]
.reg A64 [%A64_14 %A64_15 %A64_17 %A64_23 %A64_25 %A64_28 %A64_3 %A64_32 %A64_33 %A64_4 %A64_8 %out new_end]
.bbl %start # edge_out[if_1_end if_1_true] live_out[page_size size]
poparg size
mov page_size 1048576
ld.mem %A64_3 __static_1__malloc_start 0
bne %A64_3 0 if_1_end
.bbl if_1_true # edge_out[if_1_end] live_out[page_size size]
pusharg 0:A64
bsr xbrk
poparg %A64_4
st.mem __static_1__malloc_start 0 %A64_4
ld.mem %A64_8 __static_1__malloc_start 0
st.mem __static_2__malloc_end 0 %A64_8
.bbl if_1_end # edge_out[if_3_end if_3_true] live_out[page_size rounded_size]
add %U64_10 size 15
div %U64_11 %U64_10 16
shl rounded_size %U64_11 4
ld.mem %A64_14 __static_1__malloc_start 0
lea %A64_15 %A64_14 rounded_size
ld.mem %A64_17 __static_2__malloc_end 0
ble %A64_15 %A64_17 if_3_end
.bbl if_3_true # edge_out[if_2_true if_3_end] live_out[rounded_size]
add %U64_18 rounded_size page_size
sub %U64_19 %U64_18 1
div %U64_20 %U64_19 page_size
mul increment %U64_20 page_size
ld.mem %A64_23 __static_2__malloc_end 0
lea new_end %A64_23 increment
pusharg new_end
bsr xbrk
poparg %A64_25
st.mem __static_2__malloc_end 0 %A64_25
ld.mem %A64_28 __static_2__malloc_end 0
beq %A64_28 new_end if_3_end
.bbl if_2_true # edge_out[if_3_end] live_out[rounded_size]
bsr abort
.bbl if_3_end
ld.mem %out __static_1__malloc_start 0
ld.mem %A64_32 __static_1__malloc_start 0
lea %A64_33 %A64_32 rounded_size
st.mem __static_1__malloc_start 0 %A64_33
pusharg %out
ret
.fun free NORMAL [] = [A64]
.reg A64 [ptr]
.bbl %start
poparg ptr
ret
.fun mymemset NORMAL [] = [A64 S32 U64]
.reg S8 [%S8_1]
.reg S32 [i value]
.reg U64 [%U64_4 num]
.reg A64 [ptr]
.bbl %start # edge_out[for_1_cond] live_out[i num ptr value]
poparg ptr
poparg value
poparg num
mov i 0
bra for_1_cond
.bbl for_1 # edge_out[for_1_next] live_out[i num ptr value]
conv %S8_1 value
st ptr i %S8_1
.bbl for_1_next # edge_out[for_1_cond] live_out[i num ptr value]
add i i 1
.bbl for_1_cond # edge_out[for_1 for_1_exit] live_out[i num ptr value]
conv %U64_4 i
blt %U64_4 num for_1
.bbl for_1_exit
ret
.fun mymemcpy NORMAL [] = [A64 A64 U64]
.reg S8 [%S8_6]
.reg S32 [i]
.reg U64 [%U64_9 num]
.reg A64 [destination source]
.bbl %start # edge_out[for_1_cond] live_out[destination i num source]
poparg destination
poparg source
poparg num
mov i 0
bra for_1_cond
.bbl for_1 # edge_out[for_1_next] live_out[destination i num source]
ld %S8_6 source i
st destination i %S8_6
.bbl for_1_next # edge_out[for_1_cond] live_out[destination i num source]
add i i 1
.bbl for_1_cond # edge_out[for_1 for_1_exit] live_out[destination i num source]
conv %U64_9 i
blt %U64_9 num for_1
.bbl for_1_exit
ret
.fun njGetWidth NORMAL [S32] = []
.reg S32 [%out]
.bbl %start
ld.mem %out nj 24
pusharg %out
ret
.fun njGetHeight NORMAL [S32] = []
.reg S32 [%out]
.bbl %start
ld.mem %out nj 28
pusharg %out
ret
.fun njIsColor NORMAL [S32] = []
.reg U32 [%U32_18]
.bbl %start # edge_out[if_1_false if_1_true]
ld.mem %U32_18 nj 48
beq %U32_18 1 if_1_false
.bbl if_1_true
pusharg 1:S32
ret
.bbl if_1_false
pusharg 0:S32
ret
.fun njGetImage NORMAL [A64] = []
.reg U32 [%U32_21]
.reg A64 [$1_%out %out]
.bbl %start # edge_out[if_1_false if_1_true]
ld.mem %U32_21 nj 48
bne %U32_21 1 if_1_false
.bbl if_1_true
ld.mem %out nj 92
pusharg %out
ret
.bbl if_1_false
ld.mem $1_%out nj 525020
pusharg $1_%out
ret
.fun njGetImageSize NORMAL [S32] = []
.reg S32 [%S32_31 %S32_34 %S32_35 %out]
.reg U32 [%U32_36 %U32_39 %U32_40]
.bbl %start
ld.mem %S32_31 nj 24
ld.mem %S32_34 nj 28
mul %S32_35 %S32_31 %S32_34
conv %U32_36 %S32_35
ld.mem %U32_39 nj 48
mul %U32_40 %U32_36 %U32_39
conv %out %U32_40
pusharg %out
ret
.fun njClip NORMAL [U8] = [S32]
.reg S32 [x]
.reg U8 [%out]
.bbl %start # edge_out[if_2_false if_2_true] live_out[x]
poparg x
ble 0:S32 x if_2_false
.bbl if_2_true
pusharg 0:U8
ret
.bbl if_2_false # edge_out[if_1_true if_2_end] live_out[x]
ble x 255 if_2_end
.bbl if_1_true
pusharg 255:U8
ret
.bbl if_2_end
conv %out x
pusharg %out
ret
.fun njRowIDCT NORMAL [] = [A64]
.reg S32 [$1_x8 $2_x8 $3_x0 $4_x8 $5_x0 %S32_100 %S32_110 %S32_111 %S32_112 %S32_114 %S32_115 %S32_116 %S32_118 %S32_119 %S32_120 %S32_121 %S32_123 %S32_124 %S32_126 %S32_127 %S32_129 %S32_130 %S32_132 %S32_133 %S32_135 %S32_136 %S32_138 %S32_139 %S32_44 %S32_48 %S32_51 %S32_54 %S32_57 %S32_60 %S32_63 %S32_64 %S32_65 %S32_73 %S32_74 %S32_76 %S32_78 %S32_79 %S32_81 %S32_82 %S32_84 %S32_86 %S32_87 %S32_89 %S32_90 %S32_94 %S32_96 %S32_97 %S32_99 x0 x1 x2 x3 x4 x5 x6 x7 x8]
.reg A64 [blk]
.bbl %start # edge_out[if_1_end if_1_true] live_out[blk x1 x2 x3 x4 x5 x6 x7]
poparg blk
ld %S32_44 blk 16
shl x1 %S32_44 11
ld x2 blk 24
or %S32_48 x1 x2
ld x3 blk 8
or %S32_51 %S32_48 x3
ld x4 blk 4
or %S32_54 %S32_51 x4
ld x5 blk 28
or %S32_57 %S32_54 x5
ld x6 blk 20
or %S32_60 %S32_57 x6
ld x7 blk 12
or %S32_63 %S32_60 x7
bne %S32_63 0 if_1_end
.bbl if_1_true
ld %S32_64 blk 0
shl %S32_65 %S32_64 3
st blk 28 %S32_65
st blk 24 %S32_65
st blk 20 %S32_65
st blk 16 %S32_65
st blk 12 %S32_65
st blk 8 %S32_65
st blk 4 %S32_65
st blk 0 %S32_65
ret
.bbl if_1_end
ld %S32_73 blk 0
shl %S32_74 %S32_73 11
add x0 %S32_74 128
add %S32_76 x4 x5
mul x8 %S32_76 565
mov %S32_78 2276
mul %S32_79 x4 %S32_78
add x4 x8 %S32_79
mov %S32_81 3406
mul %S32_82 x5 %S32_81
sub x5 x8 %S32_82
add %S32_84 x6 x7
mul $1_x8 %S32_84 2408
mov %S32_86 799
mul %S32_87 x6 %S32_86
sub x6 $1_x8 %S32_87
mov %S32_89 4017
mul %S32_90 x7 %S32_89
sub x7 $1_x8 %S32_90
add $2_x8 x0 x1
sub $3_x0 x0 x1
add %S32_94 x3 x2
mul x1 %S32_94 1108
mov %S32_96 3784
mul %S32_97 x2 %S32_96
sub x2 x1 %S32_97
mov %S32_99 1568
mul %S32_100 x3 %S32_99
add x3 x1 %S32_100
add x1 x4 x6
sub x4 x4 x6
add x6 x5 x7
sub x5 x5 x7
add x7 $2_x8 x3
sub $4_x8 $2_x8 x3
add x3 $3_x0 x2
sub $5_x0 $3_x0 x2
add %S32_110 x4 x5
mul %S32_111 %S32_110 181
add %S32_112 %S32_111 128
shr x2 %S32_112 8
sub %S32_114 x4 x5
mul %S32_115 %S32_114 181
add %S32_116 %S32_115 128
shr x4 %S32_116 8
add %S32_118 x7 x1
shr %S32_119 %S32_118 8
st blk 0 %S32_119
add %S32_120 x3 x2
shr %S32_121 %S32_120 8
st blk 4 %S32_121
add %S32_123 $5_x0 x4
shr %S32_124 %S32_123 8
st blk 8 %S32_124
add %S32_126 $4_x8 x6
shr %S32_127 %S32_126 8
st blk 12 %S32_127
sub %S32_129 $4_x8 x6
shr %S32_130 %S32_129 8
st blk 16 %S32_130
sub %S32_132 $5_x0 x4
shr %S32_133 %S32_132 8
st blk 20 %S32_133
sub %S32_135 x3 x2
shr %S32_136 %S32_135 8
st blk 24 %S32_136
sub %S32_138 x7 x1
shr %S32_139 %S32_138 8
st blk 28 %S32_139
ret
.fun njColIDCT NORMAL [] = [A64 A64 S32]
.reg S32 [$1_x8 $2_x8 $3_x8 %S32_141 %S32_142 %S32_144 %S32_146 %S32_147 %S32_150 %S32_151 %S32_152 %S32_155 %S32_157 %S32_160 %S32_161 %S32_162 %S32_165 %S32_166 %S32_167 %S32_170 %S32_171 %S32_172 %S32_175 %S32_176 %S32_177 %S32_178 %S32_179 %S32_185 %S32_186 %S32_188 %S32_189 %S32_191 %S32_192 %S32_193 %S32_195 %S32_196 %S32_197 %S32_199 %S32_200 %S32_202 %S32_203 %S32_204 %S32_206 %S32_207 %S32_208 %S32_212 %S32_213 %S32_215 %S32_216 %S32_217 %S32_219 %S32_220 %S32_221 %S32_231 %S32_232 %S32_233 %S32_235 %S32_236 %S32_237 %S32_239 %S32_240 %S32_241 %S32_244 %S32_245 %S32_246 %S32_249 %S32_250 %S32_251 %S32_254 %S32_255 %S32_256 %S32_259 %S32_260 %S32_261 %S32_264 %S32_265 %S32_266 %S32_269 %S32_270 %S32_271 %S32_274 %S32_275 %S32_276 stride x0 x1 x2 x3 x4 x5 x6 x7 x8]
.reg U8 [%U8_180 %U8_182 %U8_242 %U8_247 %U8_252 %U8_257 %U8_262 %U8_267 %U8_272 %U8_277]
.reg A64 [blk out]
.bbl %start # edge_out[if_3_end if_3_true] live_out[blk out stride x1 x2 x3 x4 x5 x6 x7]
poparg blk
poparg out
poparg stride
mov %S32_141 32
shl %S32_142 %S32_141 2
ld %S32_144 blk %S32_142
shl x1 %S32_144 8
mov %S32_146 48
shl %S32_147 %S32_146 2
ld x2 blk %S32_147
or %S32_150 x1 x2
mov %S32_151 16
shl %S32_152 %S32_151 2
ld x3 blk %S32_152
or %S32_155 %S32_150 x3
mov %S32_157 32
ld x4 blk %S32_157
or %S32_160 %S32_155 x4
mov %S32_161 56
shl %S32_162 %S32_161 2
ld x5 blk %S32_162
or %S32_165 %S32_160 x5
mov %S32_166 40
shl %S32_167 %S32_166 2
ld x6 blk %S32_167
or %S32_170 %S32_165 x6
mov %S32_171 24
shl %S32_172 %S32_171 2
ld x7 blk %S32_172
or %S32_175 %S32_170 x7
bne %S32_175 0 if_3_end
.bbl if_3_true # edge_out[for_1_cond] live_out[out stride x0 x1]
ld %S32_176 blk 0
add %S32_177 %S32_176 32
shr %S32_178 %S32_177 6
add %S32_179 %S32_178 128
pusharg %S32_179
bsr njClip
poparg %U8_180
conv x1 %U8_180
mov x0 8
bra for_1_cond
.bbl for_1 # edge_out[for_1_next] live_out[out stride x0 x1]
conv %U8_182 x1
st out 0 %U8_182
lea out out stride
.bbl for_1_next # edge_out[for_1_cond] live_out[out stride x0 x1]
sub x0 x0 1
.bbl for_1_cond # edge_out[for_1 for_1_exit] live_out[out stride x0 x1]
bne x0 0 for_1
.bbl for_1_exit
ret
.bbl if_3_end
ld %S32_185 blk 0
shl %S32_186 %S32_185 8
add x0 %S32_186 8192
add %S32_188 x4 x5
mul %S32_189 %S32_188 565
add x8 %S32_189 4
mov %S32_191 2276
mul %S32_192 x4 %S32_191
add %S32_193 x8 %S32_192
shr x4 %S32_193 3
mov %S32_195 3406
mul %S32_196 x5 %S32_195
sub %S32_197 x8 %S32_196
shr x5 %S32_197 3
add %S32_199 x6 x7
mul %S32_200 %S32_199 2408
add $1_x8 %S32_200 4
mov %S32_202 799
mul %S32_203 x6 %S32_202
sub %S32_204 $1_x8 %S32_203
shr x6 %S32_204 3
mov %S32_206 4017
mul %S32_207 x7 %S32_206
sub %S32_208 $1_x8 %S32_207
shr x7 %S32_208 3
add $2_x8 x0 x1
sub x0 x0 x1
add %S32_212 x3 x2
mul %S32_213 %S32_212 1108
add x1 %S32_213 4
mov %S32_215 3784
mul %S32_216 x2 %S32_215
sub %S32_217 x1 %S32_216
shr x2 %S32_217 3
mov %S32_219 1568
mul %S32_220 x3 %S32_219
add %S32_221 x1 %S32_220
shr x3 %S32_221 3
add x1 x4 x6
sub x4 x4 x6
add x6 x5 x7
sub x5 x5 x7
add x7 $2_x8 x3
sub $3_x8 $2_x8 x3
add x3 x0 x2
sub x0 x0 x2
add %S32_231 x4 x5
mul %S32_232 %S32_231 181
add %S32_233 %S32_232 128
shr x2 %S32_233 8
sub %S32_235 x4 x5
mul %S32_236 %S32_235 181
add %S32_237 %S32_236 128
shr x4 %S32_237 8
add %S32_239 x7 x1
shr %S32_240 %S32_239 14
add %S32_241 %S32_240 128
pusharg %S32_241
bsr njClip
poparg %U8_242
st out 0 %U8_242
lea out out stride
add %S32_244 x3 x2
shr %S32_245 %S32_244 14
add %S32_246 %S32_245 128
pusharg %S32_246
bsr njClip
poparg %U8_247
st out 0 %U8_247
lea out out stride
add %S32_249 x0 x4
shr %S32_250 %S32_249 14
add %S32_251 %S32_250 128
pusharg %S32_251
bsr njClip
poparg %U8_252
st out 0 %U8_252
lea out out stride
add %S32_254 $3_x8 x6
shr %S32_255 %S32_254 14
add %S32_256 %S32_255 128
pusharg %S32_256
bsr njClip
poparg %U8_257
st out 0 %U8_257
lea out out stride
sub %S32_259 $3_x8 x6
shr %S32_260 %S32_259 14
add %S32_261 %S32_260 128
pusharg %S32_261
bsr njClip
poparg %U8_262
st out 0 %U8_262
lea out out stride
sub %S32_264 x0 x4
shr %S32_265 %S32_264 14
add %S32_266 %S32_265 128
pusharg %S32_266
bsr njClip
poparg %U8_267
st out 0 %U8_267
lea out out stride
sub %S32_269 x3 x2
shr %S32_270 %S32_269 14
add %S32_271 %S32_270 128
pusharg %S32_271
bsr njClip
poparg %U8_272
st out 0 %U8_272
lea out out stride
sub %S32_274 x7 x1
shr %S32_275 %S32_274 14
add %S32_276 %S32_275 128
pusharg %S32_276
bsr njClip
poparg %U8_277
st out 0 %U8_277
ret
.fun __static_1_njShowBits NORMAL [S32] = [S32]
.reg S32 [%S32_280 %S32_283 %S32_284 %S32_285 %S32_290 %S32_291 %S32_306 %S32_307 %S32_312 %S32_313 %S32_318 %S32_319 %S32_320 %S32_321 %S32_324 %S32_327 %S32_340 %S32_341 %S32_348 %S32_349 %S32_354 %S32_355 %S32_356 %S32_357 %S32_362 %S32_363 %S32_370 %S32_373 %S32_376 %S32_377 %S32_378 %S32_379 %S32_380 %out bits]
.reg U8 [marker newbyte]
.reg A64 [%A64_296 %A64_300 %A64_301 %A64_330 %A64_334 %A64_335]
.jtb switch_344_tab 256 switch_344_default [0 while_1_cond 217 switch_344_217 255 while_1_cond]
.bbl %start # edge_out[if_2_true while_1_cond] live_out[bits]
poparg bits
bne bits 0 while_1_cond
.bbl if_2_true
pusharg 0:S32
ret
.bbl while_1 # edge_out[if_3_end if_3_true] live_out[bits]
ld.mem %S32_280 nj 16
blt 0:S32 %S32_280 if_3_end
.bbl if_3_true # edge_out[while_1_cond] live_out[bits]
ld.mem %S32_283 nj 524752
shl %S32_284 %S32_283 8
or %S32_285 %S32_284 255
st.mem nj 524752 %S32_285
ld.mem %S32_290 nj 524756
add %S32_291 %S32_290 8
st.mem nj 524756 %S32_291
bra while_1_cond
.bbl if_3_end # edge_out[if_6_true while_1_cond] live_out[bits]
ld.mem %A64_296 nj 4
ld newbyte %A64_296 0
ld.mem %A64_300 nj 4
lea %A64_301 %A64_300 1
st.mem nj 4 %A64_301
ld.mem %S32_306 nj 16
sub %S32_307 %S32_306 1
st.mem nj 16 %S32_307
ld.mem %S32_312 nj 524756
add %S32_313 %S32_312 8
st.mem nj 524756 %S32_313
ld.mem %S32_318 nj 524752
shl %S32_319 %S32_318 8
conv %S32_320 newbyte
or %S32_321 %S32_319 %S32_320
st.mem nj 524752 %S32_321
conv %S32_324 newbyte
bne %S32_324 255 while_1_cond
.bbl if_6_true # edge_out[if_5_false if_5_true] live_out[bits]
ld.mem %S32_327 nj 16
beq %S32_327 0 if_5_false
.bbl if_5_true # edge_out[if_5_true_1 switch_344_default] live_out[bits marker]
ld.mem %A64_330 nj 4
ld marker %A64_330 0
ld.mem %A64_334 nj 4
lea %A64_335 %A64_334 1
st.mem nj 4 %A64_335
ld.mem %S32_340 nj 16
sub %S32_341 %S32_340 1
st.mem nj 16 %S32_341
blt 255:U8 marker switch_344_default
.bbl if_5_true_1 # edge_out[switch_344_217 switch_344_default while_1_cond while_1_cond] live_out[bits marker]
switch marker switch_344_tab
.bbl switch_344_217 # edge_out[while_1_cond] live_out[bits]
st.mem nj 16 0:S32
bra while_1_cond
.bbl switch_344_default # edge_out[if_4_false if_4_true] live_out[bits marker]
conv %S32_348 marker
and %S32_349 %S32_348 248
beq %S32_349 208 if_4_false
.bbl if_4_true # edge_out[while_1_cond] live_out[bits]
st.mem nj 0 5:S32
bra while_1_cond
.bbl if_4_false # edge_out[while_1_cond] live_out[bits]
ld.mem %S32_354 nj 524752
shl %S32_355 %S32_354 8
conv %S32_356 marker
or %S32_357 %S32_355 %S32_356
st.mem nj 524752 %S32_357
ld.mem %S32_362 nj 524756
add %S32_363 %S32_362 8
st.mem nj 524756 %S32_363
bra while_1_cond
.bbl if_5_false # edge_out[while_1_cond] live_out[bits]
st.mem nj 0 5:S32
.bbl while_1_cond # edge_out[while_1 while_1_exit] live_out[bits]
ld.mem %S32_370 nj 524756
blt %S32_370 bits while_1
.bbl while_1_exit
ld.mem %S32_373 nj 524752
ld.mem %S32_376 nj 524756
sub %S32_377 %S32_376 bits
shr %S32_378 %S32_373 %S32_377
shl %S32_379 1 bits
sub %S32_380 %S32_379 1
and %out %S32_378 %S32_380
pusharg %out
ret
.fun njSkipBits NORMAL [] = [S32]
.reg S32 [%S32_384 %S32_385 %S32_388 %S32_389 bits]
.bbl %start # edge_out[if_1_end if_1_true] live_out[bits]
poparg bits
ld.mem %S32_384 nj 524756
ble bits %S32_384 if_1_end
.bbl if_1_true # edge_out[if_1_end] live_out[bits]
pusharg bits
bsr __static_1_njShowBits
poparg %S32_385
.bbl if_1_end
ld.mem %S32_388 nj 524756
sub %S32_389 %S32_388 bits
st.mem nj 524756 %S32_389
ret
.fun njGetBits NORMAL [S32] = [S32]
.reg S32 [%out bits]
.bbl %start
poparg bits
pusharg bits
bsr __static_1_njShowBits
poparg %out
pusharg bits
bsr njSkipBits
pusharg %out
ret
.fun njByteAlign NORMAL [] = []
.reg S32 [%S32_395 %S32_396]
.bbl %start
ld.mem %S32_395 nj 524756
and %S32_396 %S32_395 248
st.mem nj 524756 %S32_396
ret
.fun __static_2_njSkip NORMAL [] = [S32]
.reg S32 [%S32_407 %S32_408 %S32_413 %S32_414 %S32_419 count]
.reg A64 [%A64_401 %A64_402]
.bbl %start # edge_out[if_1_end if_1_true]
poparg count
ld.mem %A64_401 nj 4
lea %A64_402 %A64_401 count
st.mem nj 4 %A64_402
ld.mem %S32_407 nj 16
sub %S32_408 %S32_407 count
st.mem nj 16 %S32_408
ld.mem %S32_413 nj 20
sub %S32_414 %S32_413 count
st.mem nj 20 %S32_414
ld.mem %S32_419 nj 16
ble 0:S32 %S32_419 if_1_end
.bbl if_1_true # edge_out[if_1_end]
st.mem nj 0 5:S32
.bbl if_1_end
ret
.fun njDecode16 NORMAL [U16] = [A64]
.reg S32 [%S32_423 %S32_424 %S32_427 %S32_428]
.reg U8 [%U8_422 %U8_426]
.reg U16 [%out]
.reg A64 [pos]
.bbl %start
poparg pos
ld %U8_422 pos 0
conv %S32_423 %U8_422
shl %S32_424 %S32_423 8
ld %U8_426 pos 1
conv %S32_427 %U8_426
or %S32_428 %S32_424 %S32_427
conv %out %S32_428
pusharg %out
ret
.fun __static_3_njDecodeLength NORMAL [] = []
.reg S32 [%S32_432 %S32_439 %S32_444 %S32_447]
.reg U16 [%U16_438]
.reg A64 [%A64_437]
.bbl %start # edge_out[if_4_end while_1]
ld.mem %S32_432 nj 16
ble 2:S32 %S32_432 if_4_end
.bbl while_1
st.mem nj 0 5:S32
ret
.bbl if_4_end # edge_out[if_6_end while_2]
ld.mem %A64_437 nj 4
pusharg %A64_437
bsr njDecode16
poparg %U16_438
conv %S32_439 %U16_438
st.mem nj 20 %S32_439
ld.mem %S32_444 nj 20
ld.mem %S32_447 nj 16
ble %S32_444 %S32_447 if_6_end
.bbl while_2
st.mem nj 0 5:S32
ret
.bbl if_6_end
pusharg 2:S32
bsr __static_2_njSkip
ret
.fun njSkipMarker NORMAL [] = []
.reg S32 [%S32_453]
.bbl %start
bsr __static_3_njDecodeLength
ld.mem %S32_453 nj 20
pusharg %S32_453
bsr __static_2_njSkip
ret
.fun njDecodeSOF NORMAL [] = []
.reg S32 [%S32_456 %S32_459 %S32_466 %S32_474 %S32_482 %S32_487 %S32_490 %S32_510 %S32_524 %S32_530 %S32_531 %S32_536 %S32_538 %S32_539 %S32_540 %S32_548 %S32_549 %S32_554 %S32_556 %S32_557 %S32_558 %S32_566 %S32_568 %S32_574 %S32_576 %S32_577 %S32_578 %S32_582 %S32_586 %S32_603 %S32_606 %S32_611 %S32_614 %S32_615 %S32_616 %S32_619 %S32_620 %S32_625 %S32_628 %S32_629 %S32_630 %S32_633 %S32_634 %S32_641 %S32_643 %S32_644 %S32_645 %S32_646 %S32_647 %S32_651 %S32_653 %S32_654 %S32_655 %S32_656 %S32_657 %S32_661 %S32_663 %S32_664 %S32_665 %S32_668 %S32_670 %S32_672 %S32_674 %S32_678 %S32_681 %S32_682 %S32_684 %S32_685 %S32_686 %S32_703 %S32_706 %S32_707 %S32_724 i ssxmax ssymax]
.reg U8 [%U8_465 %U8_497 %U8_523 %U8_529 %U8_547 %U8_565]
.reg U16 [%U16_473 %U16_481]
.reg U32 [%U32_498 %U32_504 %U32_511 %U32_514 %U32_515 %U32_591 %U32_594 %U32_597 %U32_694 %U32_697 %U32_700 %U32_708 %U32_711 %U32_712]
.reg U64 [%U64_687 %U64_713]
.reg A64 [%A64_464 %A64_471 %A64_472 %A64_479 %A64_480 %A64_495 %A64_522 %A64_527 %A64_545 %A64_563 %A64_688 %A64_714 %A64_719 c]
.jtb switch_505_tab 4 while_5 [1 switch_505_end 3 switch_505_end]
.bbl %start # edge_out[while_1] live_out[ssxmax ssymax]
mov ssxmax 0
mov ssymax 0
bsr __static_3_njDecodeLength
.bbl while_1 # edge_out[if_17_true while_1_cond] live_out[ssxmax ssymax]
ld.mem %S32_456 nj 0
beq %S32_456 0 while_1_cond
.bbl if_17_true
ret
.bbl while_1_cond # edge_out[while_1_exit] live_out[ssxmax ssymax]
.bbl while_1_exit # edge_out[if_20_end while_2] live_out[ssxmax ssymax]
ld.mem %S32_459 nj 20
ble 9:S32 %S32_459 if_20_end
.bbl while_2
st.mem nj 0 5:S32
ret
.bbl if_20_end # edge_out[if_22_end while_3] live_out[ssxmax ssymax]
ld.mem %A64_464 nj 4
ld %U8_465 %A64_464 0
conv %S32_466 %U8_465
beq %S32_466 8 if_22_end
.bbl while_3
st.mem nj 0 2:S32
ret
.bbl if_22_end # edge_out[branch_50 while_4] live_out[ssxmax ssymax]
ld.mem %A64_471 nj 4
lea %A64_472 %A64_471 1
pusharg %A64_472
bsr njDecode16
poparg %U16_473
conv %S32_474 %U16_473
st.mem nj 28 %S32_474
ld.mem %A64_479 nj 4
lea %A64_480 %A64_479 3
pusharg %A64_480
bsr njDecode16
poparg %U16_481
conv %S32_482 %U16_481
st.mem nj 24 %S32_482
ld.mem %S32_487 nj 24
beq %S32_487 0 while_4
.bbl branch_50 # edge_out[if_24_end while_4] live_out[ssxmax ssymax]
ld.mem %S32_490 nj 28
bne %S32_490 0 if_24_end
.bbl while_4
st.mem nj 0 5:S32
ret
.bbl if_24_end # edge_out[if_24_end_1 while_5] live_out[%U32_504 ssxmax ssymax]
ld.mem %A64_495 nj 4
ld %U8_497 %A64_495 5
conv %U32_498 %U8_497
st.mem nj 48 %U32_498
pusharg 6:S32
bsr __static_2_njSkip
ld.mem %U32_504 nj 48
blt 3:U32 %U32_504 while_5
.bbl if_24_end_1 # edge_out[switch_505_end switch_505_end while_5] live_out[ssxmax ssymax]
switch %U32_504 switch_505_tab
.bbl while_5
st.mem nj 0 2:S32
ret
.bbl switch_505_end # edge_out[if_27_end while_6] live_out[ssxmax ssymax]
ld.mem %S32_510 nj 20
conv %U32_511 %S32_510
ld.mem %U32_514 nj 48
mul %U32_515 %U32_514 3
ble %U32_515 %U32_511 if_27_end
.bbl while_6
st.mem nj 0 5:S32
ret
.bbl if_27_end # edge_out[for_15_cond] live_out[c i ssxmax ssymax]
mov i 0
lea.mem c nj 52
bra for_15_cond
.bbl for_15 # edge_out[if_29_end while_7] live_out[c i ssxmax ssymax]
ld.mem %A64_522 nj 4
ld %U8_523 %A64_522 0
conv %S32_524 %U8_523
st c 0 %S32_524
ld.mem %A64_527 nj 4
ld %U8_529 %A64_527 1
conv %S32_530 %U8_529
shr %S32_531 %S32_530 4
st c 4 %S32_531
bne %S32_531 0 if_29_end
.bbl while_7
st.mem nj 0 5:S32
ret
.bbl if_29_end # edge_out[if_31_end while_8] live_out[c i ssxmax ssymax]
ld %S32_536 c 4
ld %S32_538 c 4
sub %S32_539 %S32_538 1
and %S32_540 %S32_536 %S32_539
beq %S32_540 0 if_31_end
.bbl while_8
st.mem nj 0 2:S32
ret
.bbl if_31_end # edge_out[if_33_end while_9] live_out[c i ssxmax ssymax]
ld.mem %A64_545 nj 4
ld %U8_547 %A64_545 1
conv %S32_548 %U8_547
and %S32_549 %S32_548 15
st c 8 %S32_549
bne %S32_549 0 if_33_end
.bbl while_9
st.mem nj 0 5:S32
ret
.bbl if_33_end # edge_out[if_35_end while_10] live_out[c i ssxmax ssymax]
ld %S32_554 c 8
ld %S32_556 c 8
sub %S32_557 %S32_556 1
and %S32_558 %S32_554 %S32_557
beq %S32_558 0 if_35_end
.bbl while_10
st.mem nj 0 2:S32
ret
.bbl if_35_end # edge_out[if_37_end while_11] live_out[c i ssxmax ssymax]
ld.mem %A64_563 nj 4
ld %U8_565 %A64_563 2
conv %S32_566 %U8_565
st c 24 %S32_566
and %S32_568 %S32_566 252
beq %S32_568 0 if_37_end
.bbl while_11
st.mem nj 0 5:S32
ret
.bbl if_37_end # edge_out[if_38_end if_38_true] live_out[c i ssxmax ssymax]
pusharg 3:S32
bsr __static_2_njSkip
ld.mem %S32_574 nj 200
ld %S32_576 c 24
shl %S32_577 1 %S32_576
or %S32_578 %S32_574 %S32_577
st.mem nj 200 %S32_578
ld %S32_582 c 4
ble %S32_582 ssxmax if_38_end
.bbl if_38_true # edge_out[if_38_end] live_out[c i ssxmax ssymax]
ld ssxmax c 4
.bbl if_38_end # edge_out[for_15_next if_39_true] live_out[c i ssxmax ssymax]
ld %S32_586 c 8
ble %S32_586 ssymax for_15_next
.bbl if_39_true # edge_out[for_15_next] live_out[c i ssxmax ssymax]
ld ssymax c 8
.bbl for_15_next # edge_out[for_15_cond] live_out[c i ssxmax ssymax]
add i i 1
lea c c 48
.bbl for_15_cond # edge_out[for_15 for_15_exit] live_out[c i ssxmax ssymax]
conv %U32_591 i
ld.mem %U32_594 nj 48
blt %U32_591 %U32_594 for_15
.bbl for_15_exit # edge_out[if_41_end if_41_true] live_out[ssxmax ssymax]
ld.mem %U32_597 nj 48
bne %U32_597 1 if_41_end
.bbl if_41_true # edge_out[if_41_end] live_out[ssxmax ssymax]
mov ssymax 1
mov ssxmax 1
st.mem nj 60 1:S32
st.mem nj 56 1:S32
.bbl if_41_end # edge_out[for_16_cond] live_out[c i ssxmax ssymax]
shl %S32_603 ssxmax 3
st.mem nj 40 %S32_603
shl %S32_606 ssymax 3
st.mem nj 44 %S32_606
ld.mem %S32_611 nj 24
ld.mem %S32_614 nj 40
add %S32_615 %S32_611 %S32_614
sub %S32_616 %S32_615 1
ld.mem %S32_619 nj 40
div %S32_620 %S32_616 %S32_619
st.mem nj 32 %S32_620
ld.mem %S32_625 nj 28
ld.mem %S32_628 nj 44
add %S32_629 %S32_625 %S32_628