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refs:
- Tracking Issue for RISC-V Ratified Extensions Intrinsics #114544
- Stabilize Ratified RISC-V Target Features #116485 which was massively scaled back due to this open question
- The ABI of float types can be changed by
-Ctarget-feature
#116344 - mark some target features as 'forbidden' so they cannot be (un)set with -Ctarget-feature #129884
- Figure out which target features are required/incompatible for which ABI #131799
- Always specify
llvm_abiname
for RISC-V targets #131807
in discussion of the target modifiers RFC1, Ralf asks this question:
That's actually fine on most targets, e.g. on x86 if you set the soft-float target feature then you can enable x87 and SSE and whatnot and keep using the soft-float ABI. Only aarch64 llvm/llvm-project#110632 (from the targets I checked so far).
The interesting question is what happens on RISC-V when I disable the FP instructions on a target that usually uses the hardfloat ABI. Sadly, what LLVM usually does in that case is silently fall back to the softfloat ABI. But I haven't checked for RISC-V.
cc @beetrees
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Area: Concerning the application binary interface (ABI)Area: Floating point numbers and arithmeticCategory: This is a bug.Call for partcipation: This issues needs some investigation to determine current statusTarget: RISC-V architectureRelevant to the compiler team, which will review and decide on the PR/issue.