Description
rv8 demonstrates how RISC-V instruction emulation can benefit from JIT compilation and aggressive optimizations. However, it is dedicated to x86-64 and hard to support other host architectures, such as Apple M1 (Aarch64). SFUZZ is a high performance fuzzer using RISC-V to x86 binary translations with modern fuzzing techniques. RVVM is another example to implement tracing JIT.
The goal of this task to utilize existing JIT framework as a new abstraction layer while we accelerate RISC-V instruction executions. In particular, we would
- Avoid direct machine code generation. Instead, most operations are enforced in intermediate representation (IR) level.
- Perform common optimization techniques such as peephole optimization. ria-jit performs excellent work in regards to such optimization. See src/gen/instr/patterns.c and MEMZERO and MEMCOPY instructions proposal
- Use high-level but still efficient IR. MIR is an interesting implementation, which allows using subset of C11 for IR. SFUZZ's note Code Generation is worth reading. ETISS (Extendable Translating Instruction Set Simulator) translates binary instructions into C code and appends translated code into a block, which will be compiled and executed at runtime. As aforementioned, it is Extendable, thus it supports myriad level of customization by adopting the technique of plug-ins.
- Ensure shorter startup-time. It can be achieved by means of lightweight JIT framework and AOT compilation.
The JIT compilation's high level operation can be summed up as follows:
- Look in a hash map for a code block matching the current PC
- if a block is found
- execute this block
- if a block is not found
- allocate a new block
- invoke the translator for this block
- insert it into the hash map
- execute this block
Every block will come to an end after a branch instruction has been translated since translation occurs at the basic block level. Then, there is room for further optimization passes performed on the generated code.
We gain speed by using the technique for the reasons listed below:
- No instruction fetch
- No instruction decode
- Immediate values are baked into translated instructions
- Values of 0 can be optimized
- register x0 can be optimized
- No lookup required
- Writes are discarded
- Reduced emulation loop overhead
- Blocks can be chained based on previous branch pattern for faster lookup
Reference:
- Banshee: A Fast LLVM-Based RISC-V Binary Translator
- rv8: a high performance RISC-V to x86 binary translator / slides
- Dynamic Binary Translation for RISC-V code on x86-64 / slides / cm2 branch
- R2VM / Accelerate Cycle-Level Multi-Core RISC-V Simulation with Binary Translation
- Dynamic Binary Translator for RISC-V / riscv-dbt
- High-Performance RISC-V Emulation: LLVM-based Static Binary Translation (SBT)
- Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW / slides / HybridDBT / translationCache
- Adaptive simulation with Virtual Prototypes in an open-source RISC-V evaluation platform
- Code specialization for the MIR lightweight JIT compiler
- A Faster CRuby interpreter with dynamically specialized IR
- HIFIVE1-VP
- RISC-V static binary translator targeting AArch64 / discussion
- A Journey to the Absolute Limit: CKB-VM's LLVM AOT engine
- libriscv: RISC-V Binary Translation
- Explaining JavaScript VMs in JavaScript - Inline Caches / code: inline-cache
- Just-In-Time Compilation on ARM—A Closer Look at Call-Site Code Consistency
- LuaJIT Remake: the interpreter and the JIT tiers are automatically generated from a semantical description of the bytecodes. / Building the fastest Lua interpreter.. automatically!
- Crafting Interpreters
- How I developed a faster Ruby interpreter
- Parsing Protobuf at 2+GB/s: How I Learned To Love Tail Calls in C
- WasmNow: Fast WebAssembly Baseline Compiler
- A fast in-place interpreter for WebAssembly / wizard-engine
- Kilite: a complete example for using C2MIR
- DarkSwordVM: JIT compilation for LLVM IR
- pydrofoil: Fast RISC-V Sail emulation using PyPy/RPython's JIT compiler
- Compiling SQLite queries to native code with LLVM / LLVMSQLite
- QEMU Tiny-Code Threaded Interpreter
- MINRES: DBT-RISE: Dynamic Binary Translation (DBT) based environment to implement instruction set simulator (ISS)