From 920531310c7e1fab752734a2ef0902e1de6247d8 Mon Sep 17 00:00:00 2001 From: Philip Reames Date: Thu, 1 Feb 2024 17:52:35 -0800 Subject: [PATCH] [TTI] Use Register in isLoadFromStackSlot and isStoreToStackSlot [nfc] (#80339) (cherry picked from commit 3ff7caea330def5f8433e3eb2b89ae3fe5e9f9a0) --- llvm/include/llvm/CodeGen/TargetInstrInfo.h | 12 ++++++------ llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 4 ++-- llvm/lib/Target/AArch64/AArch64InstrInfo.h | 4 ++-- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 ++-- llvm/lib/Target/AMDGPU/SIInstrInfo.h | 4 ++-- llvm/lib/Target/ARC/ARCInstrInfo.cpp | 4 ++-- llvm/lib/Target/ARC/ARCInstrInfo.h | 4 ++-- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 8 ++++---- llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 8 ++++---- llvm/lib/Target/AVR/AVRInstrInfo.cpp | 4 ++-- llvm/lib/Target/AVR/AVRInstrInfo.h | 4 ++-- llvm/lib/Target/CSKY/CSKYInstrInfo.cpp | 4 ++-- llvm/lib/Target/CSKY/CSKYInstrInfo.h | 4 ++-- llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 4 ++-- llvm/lib/Target/Hexagon/HexagonInstrInfo.h | 4 ++-- llvm/lib/Target/Lanai/LanaiInstrInfo.cpp | 6 +++--- llvm/lib/Target/Lanai/LanaiInstrInfo.h | 6 +++--- llvm/lib/Target/Mips/Mips16InstrInfo.cpp | 4 ++-- llvm/lib/Target/Mips/Mips16InstrInfo.h | 4 ++-- llvm/lib/Target/Mips/MipsSEInstrInfo.cpp | 4 ++-- llvm/lib/Target/Mips/MipsSEInstrInfo.h | 4 ++-- llvm/lib/Target/NVPTX/NVPTXInstrInfo.h | 4 ++-- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 4 ++-- llvm/lib/Target/PowerPC/PPCInstrInfo.h | 4 ++-- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 8 ++++---- llvm/lib/Target/RISCV/RISCVInstrInfo.h | 8 ++++---- llvm/lib/Target/Sparc/SparcInstrInfo.cpp | 4 ++-- llvm/lib/Target/Sparc/SparcInstrInfo.h | 4 ++-- llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 4 ++-- llvm/lib/Target/SystemZ/SystemZInstrInfo.h | 4 ++-- llvm/lib/Target/VE/VEInstrInfo.cpp | 4 ++-- llvm/lib/Target/VE/VEInstrInfo.h | 4 ++-- llvm/lib/Target/X86/X86FrameLowering.cpp | 2 +- llvm/lib/Target/X86/X86InstrInfo.cpp | 12 ++++++------ llvm/lib/Target/X86/X86InstrInfo.h | 12 ++++++------ llvm/lib/Target/XCore/XCoreInstrInfo.cpp | 4 ++-- llvm/lib/Target/XCore/XCoreInstrInfo.h | 4 ++-- 37 files changed, 95 insertions(+), 95 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h index a113100f04e62..9032d5a85a281 100644 --- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h +++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h @@ -269,7 +269,7 @@ class TargetInstrInfo : public MCInstrInfo { /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. - virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, + virtual Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { return 0; } @@ -278,7 +278,7 @@ class TargetInstrInfo : public MCInstrInfo { /// bytes loaded from the stack. This must be implemented if a backend /// supports partial stack slot spills/loads to further disambiguate /// what the load does. - virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, + virtual Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const { MemBytes = 0; @@ -287,7 +287,7 @@ class TargetInstrInfo : public MCInstrInfo { /// Check for post-frame ptr elimination stack locations as well. /// This uses a heuristic so it isn't reliable for correctness. - virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, + virtual Register isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const { return 0; } @@ -307,7 +307,7 @@ class TargetInstrInfo : public MCInstrInfo { /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. - virtual unsigned isStoreToStackSlot(const MachineInstr &MI, + virtual Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { return 0; } @@ -316,7 +316,7 @@ class TargetInstrInfo : public MCInstrInfo { /// bytes stored to the stack. This must be implemented if a backend /// supports partial stack slot spills/loads to further disambiguate /// what the store does. - virtual unsigned isStoreToStackSlot(const MachineInstr &MI, + virtual Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const { MemBytes = 0; @@ -325,7 +325,7 @@ class TargetInstrInfo : public MCInstrInfo { /// Check for post-frame ptr elimination stack locations as well. /// This uses a heuristic, so it isn't reliable for correctness. - virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, + virtual Register isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const { return 0; } diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 2e8d8c63d6bec..9e33dcdd53d04 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -2186,7 +2186,7 @@ bool AArch64InstrInfo::isFPRCopy(const MachineInstr &MI) { return false; } -unsigned AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI, +Register AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { switch (MI.getOpcode()) { default: @@ -2210,7 +2210,7 @@ unsigned AArch64InstrInfo::isLoadFromStackSlot(const MachineInstr &MI, return 0; } -unsigned AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI, +Register AArch64InstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { switch (MI.getOpcode()) { default: diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h index db24a19fe5f8e..b79aa94076c30 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -56,9 +56,9 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo { areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override; - unsigned isLoadFromStackSlot(const MachineInstr &MI, + Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; - unsigned isStoreToStackSlot(const MachineInstr &MI, + Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; /// Does this instruction set its full destination register to zero? diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index f4ca27808a304..4b911e97d2eee 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -8526,7 +8526,7 @@ unsigned SIInstrInfo::isSGPRStackAccess(const MachineInstr &MI, return getNamedOperand(MI, AMDGPU::OpName::data)->getReg(); } -unsigned SIInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, +Register SIInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { if (!MI.mayLoad()) return Register(); @@ -8540,7 +8540,7 @@ unsigned SIInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, return Register(); } -unsigned SIInstrInfo::isStoreToStackSlot(const MachineInstr &MI, +Register SIInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { if (!MI.mayStore()) return Register(); diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index fc85b089aa471..dc9312f4180f4 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -1205,9 +1205,9 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo { unsigned isStackAccess(const MachineInstr &MI, int &FrameIndex) const; unsigned isSGPRStackAccess(const MachineInstr &MI, int &FrameIndex) const; - unsigned isLoadFromStackSlot(const MachineInstr &MI, + Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; - unsigned isStoreToStackSlot(const MachineInstr &MI, + Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; unsigned getInstBundleSize(const MachineInstr &MI) const; diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp index fe78a98837cf9..9b5e45cb5fe97 100644 --- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp +++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp @@ -65,7 +65,7 @@ static bool isStore(int Opcode) { /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. -unsigned ARCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, +Register ARCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { int Opcode = MI.getOpcode(); if (isLoad(Opcode)) { @@ -84,7 +84,7 @@ unsigned ARCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. -unsigned ARCInstrInfo::isStoreToStackSlot(const MachineInstr &MI, +Register ARCInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { int Opcode = MI.getOpcode(); if (isStore(Opcode)) { diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.h b/llvm/lib/Target/ARC/ARCInstrInfo.h index c55c9535ec296..1875aafbde826 100644 --- a/llvm/lib/Target/ARC/ARCInstrInfo.h +++ b/llvm/lib/Target/ARC/ARCInstrInfo.h @@ -37,7 +37,7 @@ class ARCInstrInfo : public ARCGenInstrInfo { /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. - unsigned isLoadFromStackSlot(const MachineInstr &MI, + Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; /// If the specified machine instruction is a direct @@ -45,7 +45,7 @@ class ARCInstrInfo : public ARCGenInstrInfo { /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. - unsigned isStoreToStackSlot(const MachineInstr &MI, + Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; unsigned getInstSizeInBytes(const MachineInstr &MI) const override; diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 4bf65be6f1026..38ea8e3b611e7 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -1304,7 +1304,7 @@ void ARMBaseInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, } } -unsigned ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI, +Register ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { switch (MI.getOpcode()) { default: break; @@ -1356,7 +1356,7 @@ unsigned ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI, return 0; } -unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI, +Register ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const { SmallVector Accesses; if (MI.mayStore() && hasStoreToStackSlot(MI, Accesses) && @@ -1555,7 +1555,7 @@ void ARMBaseInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, } } -unsigned ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, +Register ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { switch (MI.getOpcode()) { default: break; @@ -1613,7 +1613,7 @@ unsigned ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, return 0; } -unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI, +Register ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const { SmallVector Accesses; if (MI.mayLoad() && hasLoadFromStackSlot(MI, Accesses) && diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h index 6aebf3b64e8d4..e766ce7bf991e 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h @@ -186,13 +186,13 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo { /// unsigned getInstSizeInBytes(const MachineInstr &MI) const override; - unsigned isLoadFromStackSlot(const MachineInstr &MI, + Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; - unsigned isStoreToStackSlot(const MachineInstr &MI, + Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; - unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, + Register isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override; - unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, + Register isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override; void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.cpp b/llvm/lib/Target/AVR/AVRInstrInfo.cpp index 2640ad9e36267..18b7365fc5aa0 100644 --- a/llvm/lib/Target/AVR/AVRInstrInfo.cpp +++ b/llvm/lib/Target/AVR/AVRInstrInfo.cpp @@ -91,7 +91,7 @@ void AVRInstrInfo::copyPhysReg(MachineBasicBlock &MBB, } } -unsigned AVRInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, +Register AVRInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { switch (MI.getOpcode()) { case AVR::LDDRdPtrQ: @@ -110,7 +110,7 @@ unsigned AVRInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, return 0; } -unsigned AVRInstrInfo::isStoreToStackSlot(const MachineInstr &MI, +Register AVRInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { switch (MI.getOpcode()) { case AVR::STDPtrQRr: diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.h b/llvm/lib/Target/AVR/AVRInstrInfo.h index 290177f5eec66..28c0e0319d46e 100644 --- a/llvm/lib/Target/AVR/AVRInstrInfo.h +++ b/llvm/lib/Target/AVR/AVRInstrInfo.h @@ -87,9 +87,9 @@ class AVRInstrInfo : public AVRGenInstrInfo { int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, Register VReg) const override; - unsigned isLoadFromStackSlot(const MachineInstr &MI, + Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; - unsigned isStoreToStackSlot(const MachineInstr &MI, + Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; // Branch analysis. diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp index e5581bcdc3975..6baca84ab3d0a 100644 --- a/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp +++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.cpp @@ -330,7 +330,7 @@ Register CSKYInstrInfo::movImm(MachineBasicBlock &MBB, return DstReg; } -unsigned CSKYInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, +Register CSKYInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { switch (MI.getOpcode()) { default: @@ -360,7 +360,7 @@ unsigned CSKYInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, return 0; } -unsigned CSKYInstrInfo::isStoreToStackSlot(const MachineInstr &MI, +Register CSKYInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { switch (MI.getOpcode()) { default: diff --git a/llvm/lib/Target/CSKY/CSKYInstrInfo.h b/llvm/lib/Target/CSKY/CSKYInstrInfo.h index dbb69a7a87980..4e3866b1188ca 100644 --- a/llvm/lib/Target/CSKY/CSKYInstrInfo.h +++ b/llvm/lib/Target/CSKY/CSKYInstrInfo.h @@ -35,9 +35,9 @@ class CSKYInstrInfo : public CSKYGenInstrInfo { public: explicit CSKYInstrInfo(CSKYSubtarget &STI); - unsigned isLoadFromStackSlot(const MachineInstr &MI, + Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; - unsigned isStoreToStackSlot(const MachineInstr &MI, + Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; void storeRegToStackSlot(MachineBasicBlock &MBB, diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 1689b8f1e132d..feb3f872449ac 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -286,7 +286,7 @@ static bool isDuplexPairMatch(unsigned Ga, unsigned Gb) { /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. -unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, +Register HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { switch (MI.getOpcode()) { default: @@ -334,7 +334,7 @@ unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. -unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI, +Register HexagonInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { switch (MI.getOpcode()) { default: diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h index 645b57f4664df..7801e94d9959b 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h @@ -54,7 +54,7 @@ class HexagonInstrInfo : public HexagonGenInstrInfo { /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. - unsigned isLoadFromStackSlot(const MachineInstr &MI, + Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; /// If the specified machine instruction is a direct @@ -62,7 +62,7 @@ class HexagonInstrInfo : public HexagonGenInstrInfo { /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. - unsigned isStoreToStackSlot(const MachineInstr &MI, + Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; /// Check if the instruction or the bundle of instructions has diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp index aa7e8846406dd..4fe725b9457fa 100644 --- a/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp +++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.cpp @@ -710,7 +710,7 @@ unsigned LanaiInstrInfo::removeBranch(MachineBasicBlock &MBB, return Count; } -unsigned LanaiInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, +Register LanaiInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { if (MI.getOpcode() == Lanai::LDW_RI) if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() && @@ -721,7 +721,7 @@ unsigned LanaiInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, return 0; } -unsigned LanaiInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI, +Register LanaiInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const { if (MI.getOpcode() == Lanai::LDW_RI) { unsigned Reg; @@ -739,7 +739,7 @@ unsigned LanaiInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI, return 0; } -unsigned LanaiInstrInfo::isStoreToStackSlot(const MachineInstr &MI, +Register LanaiInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { if (MI.getOpcode() == Lanai::SW_RI) if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() && diff --git a/llvm/lib/Target/Lanai/LanaiInstrInfo.h b/llvm/lib/Target/Lanai/LanaiInstrInfo.h index 62f6240c6e468..189aedf07120f 100644 --- a/llvm/lib/Target/Lanai/LanaiInstrInfo.h +++ b/llvm/lib/Target/Lanai/LanaiInstrInfo.h @@ -38,13 +38,13 @@ class LanaiInstrInfo : public LanaiGenInstrInfo { bool areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, const MachineInstr &MIb) const override; - unsigned isLoadFromStackSlot(const MachineInstr &MI, + Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; - unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, + Register isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override; - unsigned isStoreToStackSlot(const MachineInstr &MI, + Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator Position, diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp index a834188e3bcc1..30ac96936de28 100644 --- a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp +++ b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp @@ -51,7 +51,7 @@ const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const { /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. -unsigned Mips16InstrInfo::isLoadFromStackSlot(const MachineInstr &MI, +Register Mips16InstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { return 0; } @@ -61,7 +61,7 @@ unsigned Mips16InstrInfo::isLoadFromStackSlot(const MachineInstr &MI, /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. -unsigned Mips16InstrInfo::isStoreToStackSlot(const MachineInstr &MI, +Register Mips16InstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { return 0; } diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.h b/llvm/lib/Target/Mips/Mips16InstrInfo.h index e57d21b48a17e..e8567ee3b9ce5 100644 --- a/llvm/lib/Target/Mips/Mips16InstrInfo.h +++ b/llvm/lib/Target/Mips/Mips16InstrInfo.h @@ -37,7 +37,7 @@ class Mips16InstrInfo : public MipsInstrInfo { /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. - unsigned isLoadFromStackSlot(const MachineInstr &MI, + Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; /// isStoreToStackSlot - If the specified machine instruction is a direct @@ -45,7 +45,7 @@ class Mips16InstrInfo : public MipsInstrInfo { /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. - unsigned isStoreToStackSlot(const MachineInstr &MI, + Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp index d76dc0143b23d..b99ddfab2a47d 100644 --- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -42,7 +42,7 @@ const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const { /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. -unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, +Register MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { unsigned Opc = MI.getOpcode(); @@ -64,7 +64,7 @@ unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. -unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI, +Register MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { unsigned Opc = MI.getOpcode(); diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.h b/llvm/lib/Target/Mips/MipsSEInstrInfo.h index 6d5a958b33f9b..a8855e26ad10f 100644 --- a/llvm/lib/Target/Mips/MipsSEInstrInfo.h +++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.h @@ -31,7 +31,7 @@ class MipsSEInstrInfo : public MipsInstrInfo { /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. - unsigned isLoadFromStackSlot(const MachineInstr &MI, + Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; /// isStoreToStackSlot - If the specified machine instruction is a direct @@ -39,7 +39,7 @@ class MipsSEInstrInfo : public MipsInstrInfo { /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. - unsigned isStoreToStackSlot(const MachineInstr &MI, + Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h index cd068a0939300..d6cbeae6984c9 100644 --- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h +++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.h @@ -34,9 +34,9 @@ class NVPTXInstrInfo : public NVPTXGenInstrInfo { * They are not implemented because the existing interface and the logic * at the caller side do not work for the elementized vector load and store. * - * virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, + * virtual Register isLoadFromStackSlot(const MachineInstr *MI, * int &FrameIndex) const; - * virtual unsigned isStoreToStackSlot(const MachineInstr *MI, + * virtual Register isStoreToStackSlot(const MachineInstr *MI, * int &FrameIndex) const; * virtual void storeRegToStackSlot(MachineBasicBlock &MBB, * MachineBasicBlock::iterator MBBI, diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 15f6b65dea83c..a9b6cd87de0e0 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -1047,7 +1047,7 @@ bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI, } } -unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, +Register PPCInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { if (llvm::is_contained(getLoadOpcodesForSpillArray(), MI.getOpcode())) { // Check for the operands added by addFrameReference (the immediate is the @@ -1101,7 +1101,7 @@ bool PPCInstrInfo::isReallyTriviallyReMaterializable( return TargetInstrInfo::isReallyTriviallyReMaterializable(MI); } -unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr &MI, +Register PPCInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { if (llvm::is_contained(getStoreOpcodesForSpillArray(), MI.getOpcode())) { if (MI.getOperand(1).isImm() && !MI.getOperand(1).getImm() && diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h index 75f9cd1c206d8..6a4d992f8d002 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h @@ -404,10 +404,10 @@ class PPCInstrInfo : public PPCGenInstrInfo { bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, Register &DstReg, unsigned &SubIdx) const override; - unsigned isLoadFromStackSlot(const MachineInstr &MI, + Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override; - unsigned isStoreToStackSlot(const MachineInstr &MI, + Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 592962cebe897..df516d7cd5c09 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -79,13 +79,13 @@ MCInst RISCVInstrInfo::getNop() const { .addImm(0); } -unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, +Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { unsigned Dummy; return isLoadFromStackSlot(MI, FrameIndex, Dummy); } -unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, +Register RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const { switch (MI.getOpcode()) { @@ -120,13 +120,13 @@ unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, return 0; } -unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI, +Register RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { unsigned Dummy; return isStoreToStackSlot(MI, FrameIndex, Dummy); } -unsigned RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI, +Register RISCVInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const { switch (MI.getOpcode()) { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h index 7e1d3f3118065..0f7d3e4e43390 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h @@ -55,13 +55,13 @@ class RISCVInstrInfo : public RISCVGenInstrInfo { MCInst getNop() const override; const MCInstrDesc &getBrCond(RISCVCC::CondCode CC) const; - unsigned isLoadFromStackSlot(const MachineInstr &MI, + Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; - unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, + Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const override; - unsigned isStoreToStackSlot(const MachineInstr &MI, + Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; - unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, + Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const override; void copyPhysRegVector(MachineBasicBlock &MBB, diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp index 90662cd87dcf1..2727a9f2efbb1 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp @@ -48,7 +48,7 @@ SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. -unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, +Register SparcInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { if (MI.getOpcode() == SP::LDri || MI.getOpcode() == SP::LDXri || MI.getOpcode() == SP::LDFri || MI.getOpcode() == SP::LDDFri || @@ -67,7 +67,7 @@ unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. -unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr &MI, +Register SparcInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { if (MI.getOpcode() == SP::STri || MI.getOpcode() == SP::STXri || MI.getOpcode() == SP::STFri || MI.getOpcode() == SP::STDFri || diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.h b/llvm/lib/Target/Sparc/SparcInstrInfo.h index 7056d6babe17b..a7bb34c6c8e77 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.h +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.h @@ -53,7 +53,7 @@ class SparcInstrInfo : public SparcGenInstrInfo { /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. - unsigned isLoadFromStackSlot(const MachineInstr &MI, + Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; /// isStoreToStackSlot - If the specified machine instruction is a direct @@ -61,7 +61,7 @@ class SparcInstrInfo : public SparcGenInstrInfo { /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. - unsigned isStoreToStackSlot(const MachineInstr &MI, + Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp index bf6547cc87ec5..f014c1a73e969 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -322,12 +322,12 @@ static int isSimpleMove(const MachineInstr &MI, int &FrameIndex, return 0; } -unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, +Register SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad); } -unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr &MI, +Register SystemZInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore); } diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h index bb883ea464d37..c72e4a5c43688 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h @@ -228,9 +228,9 @@ class SystemZInstrInfo : public SystemZGenInstrInfo { explicit SystemZInstrInfo(SystemZSubtarget &STI); // Override TargetInstrInfo. - unsigned isLoadFromStackSlot(const MachineInstr &MI, + Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; - unsigned isStoreToStackSlot(const MachineInstr &MI, + Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const override; diff --git a/llvm/lib/Target/VE/VEInstrInfo.cpp b/llvm/lib/Target/VE/VEInstrInfo.cpp index ebb9e21389c37..bc947c4f8f26d 100644 --- a/llvm/lib/Target/VE/VEInstrInfo.cpp +++ b/llvm/lib/Target/VE/VEInstrInfo.cpp @@ -413,7 +413,7 @@ void VEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. -unsigned VEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, +Register VEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { if (MI.getOpcode() == VE::LDrii || // I64 MI.getOpcode() == VE::LDLSXrii || // I32 @@ -437,7 +437,7 @@ unsigned VEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. -unsigned VEInstrInfo::isStoreToStackSlot(const MachineInstr &MI, +Register VEInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { if (MI.getOpcode() == VE::STrii || // I64 MI.getOpcode() == VE::STLrii || // I32 diff --git a/llvm/lib/Target/VE/VEInstrInfo.h b/llvm/lib/Target/VE/VEInstrInfo.h index 4fe56f24116f8..daa2b1f8aee0c 100644 --- a/llvm/lib/Target/VE/VEInstrInfo.h +++ b/llvm/lib/Target/VE/VEInstrInfo.h @@ -84,9 +84,9 @@ class VEInstrInfo : public VEGenInstrInfo { bool KillSrc) const override; /// Stack Spill & Reload { - unsigned isLoadFromStackSlot(const MachineInstr &MI, + Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; - unsigned isStoreToStackSlot(const MachineInstr &MI, + Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp index c0d358ead2787..ee59c0303e5e0 100644 --- a/llvm/lib/Target/X86/X86FrameLowering.cpp +++ b/llvm/lib/Target/X86/X86FrameLowering.cpp @@ -2067,7 +2067,7 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF, if (NeedsWinCFI) { int FI; - if (unsigned Reg = TII.isStoreToStackSlot(FrameInstr, FI)) { + if (Register Reg = TII.isStoreToStackSlot(FrameInstr, FI)) { if (X86::FR64RegClass.contains(Reg)) { int Offset; Register IgnoredFrameReg; diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index d6f9aa6d6acec..b49ef2192ccdb 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -685,13 +685,13 @@ static bool isFrameStoreOpcode(int Opcode, unsigned &MemBytes) { return false; } -unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI, +Register X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { unsigned Dummy; return X86InstrInfo::isLoadFromStackSlot(MI, FrameIndex, Dummy); } -unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI, +Register X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const { if (isFrameLoadOpcode(MI.getOpcode(), MemBytes)) @@ -700,7 +700,7 @@ unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI, return 0; } -unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI, +Register X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const { unsigned Dummy; if (isFrameLoadOpcode(MI.getOpcode(), Dummy)) { @@ -719,13 +719,13 @@ unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI, return 0; } -unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI, +Register X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { unsigned Dummy; return X86InstrInfo::isStoreToStackSlot(MI, FrameIndex, Dummy); } -unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI, +Register X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const { if (isFrameStoreOpcode(MI.getOpcode(), MemBytes)) @@ -735,7 +735,7 @@ unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI, return 0; } -unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI, +Register X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const { unsigned Dummy; if (isFrameStoreOpcode(MI.getOpcode(), Dummy)) { diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h index 939bc7daf1c7d..18c72f6fea53d 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.h +++ b/llvm/lib/Target/X86/X86InstrInfo.h @@ -243,26 +243,26 @@ class X86InstrInfo final : public X86GenInstrInfo { /// FIXME: This should become part of our instruction tables. static bool isDataInvariantLoad(MachineInstr &MI); - unsigned isLoadFromStackSlot(const MachineInstr &MI, + Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; - unsigned isLoadFromStackSlot(const MachineInstr &MI, + Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const override; /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination /// stack locations as well. This uses a heuristic so it isn't /// reliable for correctness. - unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, + Register isLoadFromStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override; - unsigned isStoreToStackSlot(const MachineInstr &MI, + Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; - unsigned isStoreToStackSlot(const MachineInstr &MI, + Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex, unsigned &MemBytes) const override; /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination /// stack locations as well. This uses a heuristic so it isn't /// reliable for correctness. - unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, + Register isStoreToStackSlotPostFE(const MachineInstr &MI, int &FrameIndex) const override; bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override; diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp index d8a8e2cddf154..ae2e0fec3f899 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp @@ -59,7 +59,7 @@ static bool isZeroImm(const MachineOperand &op) { /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. -unsigned XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, +Register XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const { int Opcode = MI.getOpcode(); if (Opcode == XCore::LDWFI) @@ -79,7 +79,7 @@ unsigned XCoreInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. -unsigned XCoreInstrInfo::isStoreToStackSlot(const MachineInstr &MI, +Register XCoreInstrInfo::isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const { int Opcode = MI.getOpcode(); if (Opcode == XCore::STWFI) diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.h b/llvm/lib/Target/XCore/XCoreInstrInfo.h index 9bf7e2dcccb7d..1dafb6ea7d211 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.h +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.h @@ -38,7 +38,7 @@ class XCoreInstrInfo : public XCoreGenInstrInfo { /// the destination along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than loading from the stack slot. - unsigned isLoadFromStackSlot(const MachineInstr &MI, + Register isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; /// isStoreToStackSlot - If the specified machine instruction is a direct @@ -46,7 +46,7 @@ class XCoreInstrInfo : public XCoreGenInstrInfo { /// the source reg along with the FrameIndex of the loaded stack slot. If /// not, return 0. This predicate must return 0 if the instruction has /// any side effects other than storing to the stack slot. - unsigned isStoreToStackSlot(const MachineInstr &MI, + Register isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,