device: LPC55xxx: add PLL0 usb fs host clock support

support kCLOCK_UsbfsSrcPll0 in CLOCK_EnableUsbfs0HostClock

Signed-off-by: Mark Wang <yichang.wang@nxp.com>

Author: MarkWangChinese

mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S16/drivers/fsl_clock.c

@@ -2068,6 +2068,32 @@ bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq)
         /* Select FRO 96 MHz */
         CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
     }
+    else if (kCLOCK_UsbfsSrcPll0 == src)
+    {
+        /*!< Configure XTAL32M */
+        POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                                /* Ensure XTAL32M is powered */
+        POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                               /* Ensure XTAL32M is powered */
+        (void)CLOCK_SetupExtClocking(16000000U);                              /* Enable clk_in clock */
+        SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;               /* Enable clk_in from XTAL32M clock  */
+        ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system  */
+
+        /*!< Set up PLL0 */
+        POWER_DisablePD(kPDRUNCFG_PD_PLL0);
+        CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
+        POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+        const pll_setup_t pll1Setup = {
+            .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(19U) | SYSCON_PLL0CTRL_SELP(9U),
+            .pllndec = SYSCON_PLL0NDEC_NDIV(1U),
+            .pllpdec = SYSCON_PLL0PDEC_PDIV(5U),
+            .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(30U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+            .pllRate = 48000000U,
+            .flags   = PLL_SETUPFLAG_WAITLOCK};
+        (void)CLOCK_SetPLL0Freq(&pll1Setup);
+
+        CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false);
+        CLOCK_AttachClk(kPLL0_to_USB0_CLK);
+        SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+    }
     else
     {
         /*!< Configure XTAL32M */

mcux/mcux-sdk-ng/devices/LPC/LPC5500/LPC55S69/drivers/fsl_clock.c

@@ -1984,6 +1984,32 @@ bool CLOCK_EnableUsbfs0HostClock(clock_usbfs_src_t src, uint32_t freq)
         /* Select FRO 96 MHz */
         CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);
     }
+    else if (kCLOCK_UsbfsSrcPll0 == src)
+    {
+        /*!< Configure XTAL32M */
+        POWER_DisablePD(kPDRUNCFG_PD_XTAL32M);                                /* Ensure XTAL32M is powered */
+        POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M);                               /* Ensure XTAL32M is powered */
+        (void)CLOCK_SetupExtClocking(16000000U);                              /* Enable clk_in clock */
+        SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK;               /* Enable clk_in from XTAL32M clock  */
+        ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system  */
+
+        /*!< Set up PLL0 */
+        POWER_DisablePD(kPDRUNCFG_PD_PLL0);
+        CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
+        POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
+        const pll_setup_t pll1Setup = {
+            .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(19U) | SYSCON_PLL0CTRL_SELP(9U),
+            .pllndec = SYSCON_PLL0NDEC_NDIV(1U),
+            .pllpdec = SYSCON_PLL0PDEC_PDIV(5U),
+            .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(30U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
+            .pllRate = 48000000U,
+            .flags   = PLL_SETUPFLAG_WAITLOCK};
+        (void)CLOCK_SetPLL0Freq(&pll1Setup);
+
+        CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false);
+        CLOCK_AttachClk(kPLL0_to_USB0_CLK);
+        SDK_DelayAtLeastUs(50U, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+    }
     else
     {
         /*!< Configure XTAL32M */