NXP RT1061 FlexSPI2 Clock Frequency Configuration Issue

[ofirshe]

Hi, I have custom board with 3 Winbond flashes on flexspi2:
`&flexspi2 {
reg = <0x402a4000 0x4000>, <0x70000000 DT_SIZE_M(192)>;
status = "okay";
pinctrl-0 = <&pinmux_flexspi2>;
pinctrl-names = "default";

/* Port A: 2 NOR Devices */
w25q512nw1: w25q512nw@0 {
    compatible = "nxp,imx-flexspi-nor";
    size = <DT_SIZE_M(64 * 8)>;
    reg = <0>;
    spi-max-frequency = <DT_FREQ_M(30)>;
    status = "okay";
    jedec-id = [ef 60 20];
    erase-block-size = <4096>;
    write-block-size = <1>;

    partitions {
        compatible = "fixed-partitions";
        #address-cells = <1>;
        #size-cells = <1>;

        w25q512nw1_partition: partition@0 {
            label = "NOR1";
            reg = <0x00000000 DT_SIZE_M(64)>;
        };
    };
};

w25q512nw2: w25q512nw@1 {
    compatible = "nxp,imx-flexspi-nor";
    size = <DT_SIZE_M(64 * 8)>;
    reg = <1>;
    spi-max-frequency = <DT_FREQ_M(30)>;
    status = "okay";
    jedec-id = [ef 60 20];
    erase-block-size = <4096>;
    write-block-size = <1>;

    partitions {
        compatible = "fixed-partitions";
        #address-cells = <1>;
        #size-cells = <1>;

        w25q512nw2_partition: partition@0 {
            label = "NOR2";
            reg = <0x00000000 DT_SIZE_M(64)>;
        };
    };
};

/* Port B: 1 NOR Device */
w25q512nw3: w25q512nw@2 {
    compatible = "nxp,imx-flexspi-nor";
    size = <DT_SIZE_M(64 * 8)>;
    reg = <2>;
    spi-max-frequency = <DT_FREQ_M(30)>;
    status = "okay";
    jedec-id = [ef 60 20];
    erase-block-size = <4096>;
    write-block-size = <1>;

    partitions {
        compatible = "fixed-partitions";
        #address-cells = <1>;
        #size-cells = <1>;

        w25q512nw3_partition: partition@0 {
            label = "NOR3";
            reg = <0x00000000 DT_SIZE_M(64)>;
        };
    };
};

};`

My goal is to set the clock frequency for these devices to 30 MHz maximum using the spi-max-frequency property. However, when I analyze the signals with a signal analyzer, I observe a frequency of 83.5 MHz on FLEXSPI2_A_SCLK signal, which does not match my configuration.
Could you please advise on what might be causing this discrepancy?

[DerekSnell]

Hi @ofirshe ,

I saw your related discussion on Discord. You shared you are already selecting CONFIG_FLASH=y. And you already found that some flash drivers call flexspi_clock_set_freq(). In your case, the driver flash_mcux_flexspi_nor.c does this by calling memc_flexspi_update_clock(), passing the spi-max-frequency as the desired frequency.

It seems like your issue is related to the clock divider. flexspi_clock_set_freq() will not change the clock source to the FlexSPI peripheral, but attempts to calculate a divider to program in CCM_CBCMR[FLEXSPI2_PODF]. I did some debugging on the MIMXRT1060-EVKC board, and stepped through this code. I see the FlexSPI2 clock is set twice using this flash driver: the first time targets 50 MHz for SFDP. The second time targets the spi-max-frequency. The debugger reports that the root_rate clock frequency to the divider is 261,818,176 Hz. For a 50 MHz target, the divider value is set to 5, which divides by 6, giving 43.7 MHz. For 30 MHz target, the divider value is 7 which is the maximum divider value. This divides by 8 for 32.8 MHz.

Since your SCLK frequency is higher than expected, I recommend you step through this code on your board to understand the root_rate clock frequency and the chosen divider. Also note that in my test, the maximum divider is not large enough with this root_rate to get SCLK below 30 MHz. You would need to configure the clock feeding the FlexSPI2 divider. The clock source to that divider is CCM_CBCMR[FLEXSPI2_CLK_SEL].

To get all the desired clock frequencies for your app, you may need to configure the clocks at the SOC level. For the RT10xx, most of these clocks are configured in clock_init() in soc.c. This is a weak function, so you can override it. Or another potential option is use the existing clock_init(), and add a CONFIG_BOARD_EARLY_INIT_HOOK for your board. That hook would execute right after soc_early_init_hook(), and before the FlexSPI/MEMC/Flash drivers are initialized.

When configuring clocks in the NXP MCUs, there is a helpful tool called MCUXpresso Clock Config Tool. This tool provides a GUI to configure all the clocks. It can generate code directly for MCUXpresso SDK projects. For Zephyr apps, that generated code does not drop in to the project yet. But you can copy the generated code needed into your Zephyr source to configure the clocks.

I am sharing some additional details here that probably do not affect your board design, but may be important in other designs. First regarding the RT1064. This derivative is the same RT1060 SOC, but integrates a QSPI flash die in the package. That QSPI flash is connected to FlexSPI2, and the RT1064 will boot and XIP from FlexSPI2. In that case, changing the FlexSPI2 clock frequency is more challenging, and should not be done while XIPing. The other RT106x derivatives boot and execute from the primary FlexSPI instance, and in ofirshe's case the FlexSPI2 clock can be easily changed in the startup code while XIPing from the primary FlexSPI interface.

The FlexSPI peripheral drives the output signal SCLK to the external memory. SCLK is derived from the internal serial root clock, which for FlexSPI2 is the output of the CCM_CBCMR[FLEXSPI2_PODF] divider. It appears ofirshe is using a Single Data Rate (SDR) QSPI flash here. With SDR, the SCLK output frequency is equal to the serial root clock frequency. With Double Data Rate (DDR) memories, the output SCLK frequency is half the serial root clock frequency.

Best regards

[ofirshe]

Thanks, @DerekSnell.

Following your advice, I was able to successfully configure the FlexSPI2 output clock.