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Vexriscv dual-core smp architecture has a problem when debugging

Status: Open.

#446 In SpinalHDL/VexRiscv;

· TieTouXiaoGe opened on Mar 11, 2025

Inquiry on running Dhrystone benchmark flow on VexRiscv

Status: Open.

#445 In SpinalHDL/VexRiscv;

· nerdylye opened on Mar 4, 2025

Partitioning On-Chip RAM in Murax SoC and Mapping IP Access

Status: Open.

#443 In SpinalHDL/VexRiscv;

· xavier-design opened on Feb 12, 2025

Any way to replace 'Area' with 'Component' in plugin's implementation?

Status: Open.

#441 In SpinalHDL/VexRiscv;

· davine47 opened on Jan 21, 2025

How to add extra memory to proessor

Status: Open.

#439 In SpinalHDL/VexRiscv;

· karegoud opened on Jan 14, 2025

custom FPU

Status: Open.

#438 In SpinalHDL/VexRiscv;

· ztachip opened on Jan 14, 2025

Regarding the regression test...

Status: Open.

#437 In SpinalHDL/VexRiscv;

· nerdylye opened on Dec 26, 2024

Do you have plan to add FPU area timing option for vexriscv like vexii?

Status: Open.

#436 In SpinalHDL/VexRiscv;

· littlezpf666 opened on Dec 25, 2024

VexRiscv for custom processing in memory instructions

Status: Open.

#420 In SpinalHDL/VexRiscv;

· neha2351 opened on Aug 7, 2024

AxiCrossBar with Standard Axi4 Interface in Briey

Status: Open.

#406 In SpinalHDL/VexRiscv;

· ic-hjx opened on May 6, 2024

How to only modify certain one reset kind of specific Reg in vex core.

Status: Open.

#404 In SpinalHDL/VexRiscv;

· littlezpf666 opened on Apr 22, 2024

Compile C code and run bare metal cycle accurate simulation

Status: Open.

#395 In SpinalHDL/VexRiscv;

· nachiket opened on Mar 6, 2024