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A digital design project for a MIPS Reduced Instruction Set Computer (RISC) single-cycle processor design that supports 32-bit MIPS instructions with an 8-bit wide datapath, on a 256x32 ROM and 256x8 RAM, implemented through structural VHDL
algorhtym/mips-single-cycle-processor
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A digital design project for a MIPS Reduced Instruction Set Computer (RISC) single-cycle processor design that supports 32-bit MIPS instructions with an 8-bit wide datapath, on a 256x32 ROM and 256x8 RAM, implemented through structural VHDL
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