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| 1 | +.. SPDX-License-Identifier: GPL-2.0-or-later |
| 2 | +
|
| 3 | +Kernel driver max42500 |
| 4 | +====================== |
| 5 | + |
| 6 | +Supported chips: |
| 7 | + * Analog Devices MAX42500 |
| 8 | + |
| 9 | + Prefix: 'max42500' |
| 10 | + |
| 11 | + Addresses scanned: I2C 0x28 to 0x2B |
| 12 | + |
| 13 | + Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/max42500.pdf |
| 14 | + |
| 15 | +Author: Kent Libetario <Kent.Libetario@analog.com> |
| 16 | + |
| 17 | +Description |
| 18 | +----------- |
| 19 | + |
| 20 | +This driver supports hardware monitoring of MAX42500 power system with up |
| 21 | +to seven voltage monitor inputs. Each input has programmable overvoltage |
| 22 | +(OV) and undervoltage (UV) thresholds where two of the inputs support |
| 23 | +dynamic voltage scaling (DVS). Additionally, the MAX42500 features a |
| 24 | +programmable flexible power sequence recorder that stores timestamps |
| 25 | +separately. And also, the MAX42500 has a programmable challenge and |
| 26 | +response watchdog with a configurable RESET output. |
| 27 | + |
| 28 | + |
| 29 | +Usage Notes |
| 30 | +----------- |
| 31 | + |
| 32 | +This driver does not auto-detect devices. You will have to instantiate the |
| 33 | +devices explicitly. Please see Documentation/i2c/instantiating-devices.rst |
| 34 | +for details. |
| 35 | + |
| 36 | +Due to its multi-functionality, the MAX42500 is split into three drivers: |
| 37 | +the mfd driver as the main device, and the hwmon and watchdog drivers as |
| 38 | +the sub-devices. The mfd driver is a client to the core driver and |
| 39 | +consumed by both the hwmon and watchdog drivers. |
| 40 | + |
| 41 | +Optionally, two power management GPIOs are provided by the mfd driver and |
| 42 | +consumed only by the hwmon sub-device driver. The pins are fixed-outputs |
| 43 | +to control the voltage monitor comparators and trigger the power sequence |
| 44 | +timestamp recording of the device. Please see the datasheet for details. |
| 45 | + |
| 46 | +For the two GPIO output pins to be consumed, the device tree will look |
| 47 | +like this: |
| 48 | + |
| 49 | +.. code-block:: |
| 50 | +
|
| 51 | + i2c { |
| 52 | + #address-cells = <1>; |
| 53 | + #size-cells = <0>; |
| 54 | + poweroff-gpios |
| 55 | + sleepoff-gpios |
| 56 | +
|
| 57 | + hwmon@28 { |
| 58 | + compatible = "adi,max42500"; |
| 59 | + reg = <0x28>; |
| 60 | + }; |
| 61 | + }; |
| 62 | +
|
| 63 | +Otherwise, the two pins maybe omitted in the device tree if unused. |
| 64 | + |
| 65 | + |
| 66 | +Platform data support |
| 67 | +--------------------- |
| 68 | + |
| 69 | +The Hwmon driver supports standard Hwmon ABI driver and sysfs platform |
| 70 | +data. While the watchdog driver supports the standard watchdog ABI driver |
| 71 | +and sysfs platform data. |
| 72 | + |
| 73 | + |
| 74 | +Hwmon Sysfs entries |
| 75 | +------------------- |
| 76 | + |
| 77 | +The following attributes are supported. Limits are read-write; all other |
| 78 | +attributes are read-only. |
| 79 | + |
| 80 | + |
| 81 | +Chip |
| 82 | +~~~~ |
| 83 | + |
| 84 | +======================= ======================================================= |
| 85 | +chip_pec Enable or disable PEC: PECE bit in CONFIG1 register |
| 86 | +======================= ======================================================= |
| 87 | + |
| 88 | +In |
| 89 | +~~ |
| 90 | + |
| 91 | +======================= ====================================================== |
| 92 | +in[1-7]_label "VMON[1-7]" |
| 93 | +in[1-7]_enable Enable or disable voltage monitors: VM1 to VM7 bits of |
| 94 | + VMON register |
| 95 | +in[1-5]_min Nominal Voltage set point: VIN1 to VIN5 registers |
| 96 | +in[1-5]_lcrit IN1-IN5 UV threshold: UV1 to UV5 nibbles of OVUV1 to |
| 97 | + OVUV5 registers |
| 98 | +in[6-7]_lcrit IN6-IN7 UV threshold: VINU6 to VINU7 registers |
| 99 | +in[1-5]_crit IN1-IN5 OV threshold: OV1 to OV5 nibbles of OVUV1 to |
| 100 | + OVUV5 registers |
| 101 | +in[6-7]_crit IN6-IN7 OV threshold: VINO6 to VINO7 registers |
| 102 | +in[1-7]_reset_history Enable or disable reset mapping: IN1 to IN7 bits of |
| 103 | + RSTMAP register |
| 104 | +======================= ====================================================== |
| 105 | + |
| 106 | +Power |
| 107 | +~~~~~ |
| 108 | + |
| 109 | +=============================== =============================================== |
| 110 | +power[1-7]_label "STATUS[1-7]" |
| 111 | +power_enable OFF comparator status: STATOFF register |
| 112 | +power_lcrit_alarm UV comparator status: STATUV register |
| 113 | +power_crit_alarm OV comparator status: STATOV register |
| 114 | +power[1-7]_average_interval_min Power-Down sequence time-stamp: DTIME1 to |
| 115 | + DTIME7 registers |
| 116 | +power[1-7]_average_interval_max Power-Up sequence time-stamp: UTIME1 to |
| 117 | + UTIME7 registers |
| 118 | +=============================== =============================================== |
| 119 | + |
| 120 | + |
| 121 | +Watchdog Sysfs entries |
| 122 | +---------------------- |
| 123 | + |
| 124 | +======================= ======================================================= |
| 125 | +start Enable the watchdog: WDEN bit of WDCFG2 register |
| 126 | +stop Disable the watchdog: WDEN bit of WDCFG2 register |
| 127 | +ping Set the watchdog key to the device: WDKEY register |
| 128 | +status Watchdog status: WDSTAT register |
| 129 | +set_timeout Watchdog Clock Divider: WDIV bits of WDCDIV register |
| 130 | +set_pretimeout First Update Extension: 1UD bit of WDCFG2 register |
| 131 | +restart Reset Hold or Active Timeout: RHLD bits of RSTCTRL |
| 132 | + register |
| 133 | +======================= ======================================================= |
| 134 | + |
| 135 | +.. |
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