This repository provides an implementation of a Finite Impulse Response (FIR) filter for image processing. The project is developed using VHDL for FPGA deployment and Octave for simulation and validation.
Special thanks to Marco Winzker (Professor) and FPGA Vision for their valuable insights and contributions to this project. Their expertise in FPGA design and image processing served as a foundation for this implementation.
The FIR filter is designed to perform image processing operations such as smoothing, edge detection, or noise reduction. The project demonstrates how a digital filter can be simulated, tested, and implemented for real-time processing on an FPGA.
Octave Simulation: Analyze and verify filter characteristics (frequency response, impulse response) and apply filtering on test images. FPGA Implementation: Efficient hardware implementation of the FIR filter for real-time image processing.
Configurable Parameters: Filter coefficients. Input image dimensions. Bit precision for fixed-point arithmetic.
Contributions are welcome! If you'd like to improve this project, fix bugs, or add new features, feel free to fork the repository, make your changes, and submit a pull request. Your efforts will help make this trading application even better!
If you found this project helpful or learned something new from it, you can support the development with just a cup of coffee ☕. It's always appreciated and keeps the ideas flowing!
