Skip to content

[HLSL] Run finalize linkage pass for all targets #134260

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 1 commit into
base: main
Choose a base branch
from
Open

[HLSL] Run finalize linkage pass for all targets #134260

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
6 changes: 6 additions & 0 deletions clang/lib/CodeGen/BackendUtil.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -56,6 +56,7 @@
#include "llvm/Target/TargetOptions.h"
#include "llvm/TargetParser/SubtargetFeature.h"
#include "llvm/TargetParser/Triple.h"
#include "llvm/Transforms/HLSL/HLSLFinalizeLinkage.h"
#include "llvm/Transforms/HipStdPar/HipStdPar.h"
#include "llvm/Transforms/IPO/EmbedBitcodePass.h"
#include "llvm/Transforms/IPO/LowerTypeTests.h"
Expand Down Expand Up @@ -1115,6 +1116,11 @@ void EmitAssemblyHelper::RunOptimizationPipeline(
if (CodeGenOpts.LinkBitcodePostopt)
MPM.addPass(LinkInModulesPass(BC));

if (LangOpts.HLSL && !CodeGenOpts.DisableLLVMPasses) {
// Passes required by HLSL for every backend.
MPM.addPass(HLSLFinalizeLinkage());
}

// Add a verifier pass if requested. We don't have to do this if the action
// requires code generation because there will already be a verifier pass in
// the code-generation pipeline.
Expand Down
1 change: 1 addition & 0 deletions clang/lib/CodeGen/CMakeLists.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@ set(LLVM_LINK_COMPONENTS
FrontendOpenMP
FrontendOffloading
HIPStdPar
HLSL
IPO
IRPrinter
IRReader
Expand Down
2 changes: 1 addition & 1 deletion clang/test/CodeGenHLSL/builtins/D3DCOLORtoUBYTE4.hlsl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
// RUN: -emit-llvm -O1 -o - | FileCheck %s --check-prefixes=CHECK

// CHECK-LABEL: D3DCOLORtoUBYTE4
int4 test_D3DCOLORtoUBYTE4(float4 p1) {
export int4 test_D3DCOLORtoUBYTE4(float4 p1) {
// CHECK: %[[SCALED:.*]] = fmul [[FMFLAGS:.*]][[FLOAT_TYPE:<4 x float>]] %{{.*}}, splat (float 0x406FE01000000000)
// CHECK: %[[CONVERTED:.*]] = fptoui [[FLOAT_TYPE]] %[[SCALED]] to [[INT_TYPE:<4 x i32>]]
// CHECK: %[[SHUFFLED:.*]] = shufflevector [[INT_TYPE]] %[[CONVERTED]], [[INT_TYPE]] poison, <4 x i32> <i32 2, i32 1, i32 0, i32 3>
Expand Down
12 changes: 6 additions & 6 deletions clang/test/CodeGenHLSL/builtins/and.hlsl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@
// CHECK-NEXT: [[HLSL_AND:%.*]] = and i1 [[X]], [[Y]]
// CHECK-NEXT: ret i1 [[HLSL_AND]]
//
bool test_and_scalar(bool x, bool y) {
export bool test_and_scalar(bool x, bool y) {
return and(x, y);
}

Expand All @@ -19,7 +19,7 @@ bool test_and_scalar(bool x, bool y) {
// CHECK-NEXT: [[HLSL_AND:%.*]] = and <2 x i1> [[X]], [[Y]]
// CHECK-NEXT: ret <2 x i1> [[HLSL_AND]]
//
bool2 test_and_bool2(bool2 x, bool2 y) {
export bool2 test_and_bool2(bool2 x, bool2 y) {
return and(x, y);
}

Expand All @@ -29,7 +29,7 @@ bool2 test_and_bool2(bool2 x, bool2 y) {
// CHECK-NEXT: [[HLSL_AND:%.*]] = and <3 x i1> [[X]], [[Y]]
// CHECK-NEXT: ret <3 x i1> [[HLSL_AND]]
//
bool3 test_and_bool3(bool3 x, bool3 y) {
export bool3 test_and_bool3(bool3 x, bool3 y) {
return and(x, y);
}

Expand All @@ -39,7 +39,7 @@ bool3 test_and_bool3(bool3 x, bool3 y) {
// CHECK-NEXT: [[HLSL_AND:%.*]] = and <4 x i1> [[X]], [[Y]]
// CHECK-NEXT: ret <4 x i1> [[HLSL_AND]]
//
bool4 test_and_bool4(bool4 x, bool4 y) {
export bool4 test_and_bool4(bool4 x, bool4 y) {
return and(x, y);
}

Expand All @@ -51,7 +51,7 @@ bool4 test_and_bool4(bool4 x, bool4 y) {
// CHECK-NEXT: [[HLSL_AND:%.*]] = and <4 x i1> [[TOBOOL]], [[TOBOOL1]]
// CHECK-NEXT: ret <4 x i1> [[HLSL_AND]]
//
bool4 test_and_int4(int4 x, int4 y) {
export bool4 test_and_int4(int4 x, int4 y) {
return and(x, y);
}

Expand All @@ -63,6 +63,6 @@ bool4 test_and_int4(int4 x, int4 y) {
// CHECK-NEXT: [[HLSL_AND:%.*]] = and <4 x i1> [[TOBOOL]], [[TOBOOL1]]
// CHECK-NEXT: ret <4 x i1> [[HLSL_AND]]
//
bool4 test_and_float4(float4 x, float4 y) {
export bool4 test_and_float4(float4 x, float4 y) {
return and(x, y);
}
12 changes: 6 additions & 6 deletions clang/test/CodeGenHLSL/builtins/asfloat.hlsl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2,39 +2,39 @@

// CHECK: define {{.*}}test_uint{{.*}}(i32 {{.*}} [[VAL:%.*]]){{.*}}
// CHECK: bitcast i32 [[VAL]] to float
float test_uint(uint p0) {
export float test_uint(uint p0) {
return asfloat(p0);
}

// CHECK: define {{.*}}test_int{{.*}}(i32 {{.*}} [[VAL:%.*]]){{.*}}
// CHECK: bitcast i32 [[VAL]] to float
float test_int(int p0) {
export float test_int(int p0) {
return asfloat(p0);
}

// CHECK: define {{.*}}test_float{{.*}}(float {{.*}} [[VAL:%.*]]){{.*}}
// CHECK-NOT: bitcast
// CHECK: ret float [[VAL]]
float test_float(float p0) {
export float test_float(float p0) {
return asfloat(p0);
}

// CHECK: define {{.*}}test_vector_uint{{.*}}(<4 x i32> {{.*}} [[VAL:%.*]]){{.*}}
// CHECK: bitcast <4 x i32> [[VAL]] to <4 x float>

float4 test_vector_uint(uint4 p0) {
export float4 test_vector_uint(uint4 p0) {
return asfloat(p0);
}

// CHECK: define {{.*}}test_vector_int{{.*}}(<4 x i32> {{.*}} [[VAL:%.*]]){{.*}}
// CHECK: bitcast <4 x i32> [[VAL]] to <4 x float>
float4 test_vector_int(int4 p0) {
export float4 test_vector_int(int4 p0) {
return asfloat(p0);
}

// CHECK: define {{.*}}test_vector_float{{.*}}(<4 x float> {{.*}} [[VAL:%.*]]){{.*}}
// CHECK-NOT: bitcast
// CHECK: ret <4 x float> [[VAL]]
float4 test_vector_float(float4 p0) {
export float4 test_vector_float(float4 p0) {
return asfloat(p0);
}
12 changes: 6 additions & 6 deletions clang/test/CodeGenHLSL/builtins/asint.hlsl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,39 +3,39 @@
// CHECK: define {{.*}}test_int{{.*}}(i32 {{.*}} [[VAL:%.*]]){{.*}}
// CHECK-NOT: bitcast
// CHECK: ret i32 [[VAL]]
int test_int(int p0) {
export int test_int(int p0) {
return asint(p0);
}

// CHECK: define {{.*}}test_uint{{.*}}(i32 {{.*}} [[VAL:%.*]]){{.*}}
// CHECK-NOT: bitcast
// CHECK: ret i32 [[VAL]]
int test_uint(uint p0) {
export int test_uint(uint p0) {
return asint(p0);
}

// CHECK: define {{.*}}test_float{{.*}}(float {{.*}} [[VAL:%.*]]){{.*}}
// CHECK: bitcast float [[VAL]] to i32
int test_float(float p0) {
export int test_float(float p0) {
return asint(p0);
}

// CHECK: define {{.*}}test_vector_int{{.*}}(<4 x i32> {{.*}} [[VAL:%.*]]){{.*}}
// CHECK-NOT: bitcast
// CHECK: ret <4 x i32> [[VAL]]
int4 test_vector_int(int4 p0) {
export int4 test_vector_int(int4 p0) {
return asint(p0);
}

// CHECK: define {{.*}}test_vector_uint{{.*}}(<4 x i32> {{.*}} [[VAL:%.*]]){{.*}}
// CHECK-NOT: bitcast
// CHECK: ret <4 x i32> [[VAL]]
int4 test_vector_uint(uint4 p0) {
export int4 test_vector_uint(uint4 p0) {
return asint(p0);
}

// CHECK: define {{.*}}test_vector_float{{.*}}(<4 x float> {{.*}} [[VAL:%.*]]){{.*}}
// CHECK: bitcast <4 x float> [[VAL]] to <4 x i32>
int4 test_vector_float(float4 p0) {
export int4 test_vector_float(float4 p0) {
return asint(p0);
}
12 changes: 6 additions & 6 deletions clang/test/CodeGenHLSL/builtins/asint16.hlsl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
//CHECK-NOT: bitcast
//CHECK: entry:
//CHECK-NEXT: ret i16 [[VAL]]
int16_t test_int(int16_t p0)
export int16_t test_int(int16_t p0)
{
return asint16(p0);
}
Expand All @@ -15,7 +15,7 @@ int16_t test_int(int16_t p0)
//CHECK-NOT:bitcast
//CHECK: entry:
//CHECK-NEXT: ret i16 [[VAL]]
int16_t test_uint(uint16_t p0)
export int16_t test_uint(uint16_t p0)
{
return asint16(p0);
}
Expand All @@ -24,7 +24,7 @@ int16_t test_uint(uint16_t p0)
//CHECK-SAME: {{.*}}(half {{.*}} [[VAL:%.*]]){{.*}}
//CHECK: [[RES:%.*]] = bitcast half [[VAL]] to i16
//CHECK-NEXT : ret i16 [[RES]]
int16_t test_half(half p0)
export int16_t test_half(half p0)
{
return asint16(p0);
}
Expand All @@ -34,7 +34,7 @@ int16_t test_half(half p0)
//CHECK-NOT: bitcast
//CHECK: entry:
//CHECK-NEXT: ret <4 x i16> [[VAL]]
int16_t4 test_vector_int(int16_t4 p0)
export int16_t4 test_vector_int(int16_t4 p0)
{
return asint16(p0);
}
Expand All @@ -44,7 +44,7 @@ int16_t4 test_vector_int(int16_t4 p0)
//CHECK-NOT: bitcast
//CHECK-NEXT: entry:
//CHECK-NEXT: ret <4 x i16> [[VAL]]
int16_t4 test_vector_uint(uint16_t4 p0)
export int16_t4 test_vector_uint(uint16_t4 p0)
{
return asint16(p0);
}
Expand All @@ -53,7 +53,7 @@ int16_t4 test_vector_uint(uint16_t4 p0)
//CHECK-SAME: {{.*}}(<4 x half> {{.*}} [[VAL:%.*]]){{.*}}
//CHECK: [[RES:%.*]] = bitcast <4 x half> [[VAL]] to <4 x i16>
//CHECK-NEXT: ret <4 x i16> [[RES]]
int16_t4 fn(half4 p1)
export int16_t4 fn(half4 p1)
{
return asint16(p1);
}
Expand Down
12 changes: 6 additions & 6 deletions clang/test/CodeGenHLSL/builtins/asuint.hlsl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,39 +3,39 @@
// CHECK: define {{.*}}test_uint{{.*}}(i32 {{.*}} [[VAL:%.*]]){{.*}}
// CHECK-NOT: bitcast
// CHECK: ret i32 [[VAL]]
uint test_uint(uint p0) {
export uint test_uint(uint p0) {
return asuint(p0);
}

// CHECK: define {{.*}}test_int{{.*}}(i32 {{.*}} [[VAL:%.*]]){{.*}}
// CHECK-NOT: bitcast
// CHECK: ret i32 [[VAL]]
uint test_int(int p0) {
export uint test_int(int p0) {
return asuint(p0);
}

// CHECK: define {{.*}}test_float{{.*}}(float {{.*}} [[VAL:%.*]]){{.*}}
// CHECK: bitcast float [[VAL]] to i32
uint test_float(float p0) {
export uint test_float(float p0) {
return asuint(p0);
}

// CHECK: define {{.*}}test_vector_uint{{.*}}(<4 x i32> {{.*}} [[VAL:%.*]]){{.*}}
// CHECK-NOT: bitcast
// CHECK: ret <4 x i32> [[VAL]]
uint4 test_vector_uint(uint4 p0) {
export uint4 test_vector_uint(uint4 p0) {
return asuint(p0);
}

// CHECK: define {{.*}}test_vector_int{{.*}}(<4 x i32> {{.*}} [[VAL:%.*]]){{.*}}
// CHECK-NOT: bitcast
// CHECK: ret <4 x i32> [[VAL]]
uint4 test_vector_int(int4 p0) {
export uint4 test_vector_int(int4 p0) {
return asuint(p0);
}

// CHECK: define {{.*}}test_vector_float{{.*}}(<4 x float> {{.*}} [[VAL:%.*]]){{.*}}
// CHECK: bitcast <4 x float> [[VAL]] to <4 x i32>
uint4 test_vector_float(float4 p0) {
export uint4 test_vector_float(float4 p0) {
return asuint(p0);
}
12 changes: 6 additions & 6 deletions clang/test/CodeGenHLSL/builtins/asuint16.hlsl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
//CHECK-NOT: bitcast
//CHECK: entry:
//CHECK: ret i16 [[VAL]]
uint16_t test_int(int16_t p0)
export uint16_t test_int(int16_t p0)
{
return asuint16(p0);
}
Expand All @@ -15,7 +15,7 @@ uint16_t test_int(int16_t p0)
//CHECK-NOT: bitcast
//CHECK: entry:
//CHECK-NEXT: ret i16 [[VAL]]
uint16_t test_uint(uint16_t p0)
export uint16_t test_uint(uint16_t p0)
{
return asuint16(p0);
}
Expand All @@ -24,7 +24,7 @@ uint16_t test_uint(uint16_t p0)
//CHECK-SAME: {{.*}}(half {{.*}} [[VAL:%.*]]){{.*}}
//CHECK: [[RES:%.*]] = bitcast half [[VAL]] to i16
//CHECK-NEXT: ret i16 [[RES]]
uint16_t test_half(half p0)
export uint16_t test_half(half p0)
{
return asuint16(p0);
}
Expand All @@ -34,7 +34,7 @@ uint16_t test_half(half p0)
//CHECK-NOT: bitcast
//CHECK: entry:
//CHECK-NEXT: ret <4 x i16> [[VAL]]
uint16_t4 test_vector_int(int16_t4 p0)
export uint16_t4 test_vector_int(int16_t4 p0)
{
return asuint16(p0);
}
Expand All @@ -44,7 +44,7 @@ uint16_t4 test_vector_int(int16_t4 p0)
//CHECK-NOT: bitcast
//CHECK: entry:
//CHECK-NEXT: ret <4 x i16> [[VAL]]
uint16_t4 test_vector_uint(uint16_t4 p0)
export uint16_t4 test_vector_uint(uint16_t4 p0)
{
return asuint16(p0);
}
Expand All @@ -53,7 +53,7 @@ uint16_t4 test_vector_uint(uint16_t4 p0)
//CHECK-SAME: {{.*}}(<4 x half> {{.*}} [[VAL:%.*]]){{.*}}
//CHECK: [[RES:%.*]] = bitcast <4 x half> [[VAL]] to <4 x i16>
//CHECK-NEXT: ret <4 x i16> [[RES]]
uint16_t4 fn(half4 p1)
export uint16_t4 fn(half4 p1)
{
return asuint16(p1);
}
Expand Down
4 changes: 2 additions & 2 deletions clang/test/CodeGenHLSL/builtins/clip.hlsl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
// RUN: %clang_cc1 -finclude-default-header -triple spirv-vulkan-pixel %s -fnative-half-type -emit-llvm -o - | FileCheck %s --check-prefix=SPIRV


void test_scalar(float Buf) {
export void test_scalar(float Buf) {
// CHECK: define void @{{.*}}test_scalar{{.*}}(float {{.*}} [[VALP:%.*]])
// CHECK: [[LOAD:%.*]] = load float, ptr [[VALP]].addr, align 4
// CHECK-NEXT: [[FCMP:%.*]] = fcmp reassoc nnan ninf nsz arcp afn olt float [[LOAD]], 0.000000e+00
Expand All @@ -20,7 +20,7 @@ void test_scalar(float Buf) {
clip(Buf);
}

void test_vector4(float4 Buf) {
export void test_vector4(float4 Buf) {
// CHECK: define void @{{.*}}test_vector{{.*}}(<4 x float> {{.*}} [[VALP:%.*]])
// CHECK: [[LOAD:%.*]] = load <4 x float>, ptr [[VALP]].addr, align 16
// CHECK-NEXT: [[FCMP:%.*]] = fcmp reassoc nnan ninf nsz arcp afn olt <4 x float> [[LOAD]], zeroinitializer
Expand Down
Loading
Loading