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[X86][DAGCombiner][SelectionDAG] - Fold Zext Build Vector to Bitcast of widen Build Vector #135010

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[X86][DAGCombiner][SelectionDAG] - Fold Zext Build Vector to Bitcast of widen Build Vector #135010

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e5c1914
[X86][DAGCombiner][SelectionDAG] - Fold Zext Build Vector to Bitcast …
Apr 9, 2025
483c273
Fix for test cases failure
Apr 16, 2025
a48660c
Merge branch 'llvm:main' into ZextBuildVec
rohitaggarwal007 Apr 25, 2025
ff669c6
Fix for the test case failure
Apr 25, 2025
e776464
Merge branch 'llvm:main' into ZextBuildVec
rohitaggarwal007 Apr 29, 2025
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68 changes: 68 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Expand Up @@ -14295,6 +14295,71 @@ static SDValue widenAbs(SDNode *Extend, SelectionDAG &DAG) {
return DAG.getZExtOrTrunc(NewAbs, SDLoc(Extend), VT);
}

// Try to widen the build vector and bitcast it to the type of zext.
// This is a special case for the 128-bit vector types. Intention is to remove
// the zext and replace it with a bitcast the wider type. While lowering
// the bitcast is removed and extra commutation due to zext is avoided.
// For example:
// zext v4i16 ( v4i8 build_vector (x, y, z, w)) -> bitcast v4i16 ( v8i8
// build_vector (x, 0, y, 0, z, w, 0)
static SDValue widenBuildVec(SDNode *Extend, SelectionDAG &DAG) {

assert(Extend->getOpcode() == ISD::ZERO_EXTEND && "Expected zero extend.");

EVT ExtendVT = Extend->getValueType(0);

SDValue BV = Extend->getOperand(0);
if (BV.getOpcode() != ISD::BUILD_VECTOR || !BV.hasOneUse())
return SDValue();

if (any_of(BV->op_values(), [](SDValue Op) { return Op.isUndef(); })) {
// If the build vector has undef elements, we cannot widen it.
// The widening would create a vector with more undef elements, which
// is not valid.
return SDValue();
}

SDLoc dl(BV);
EVT VT = BV.getValueType();
EVT EltVT = BV.getOperand(0).getValueType();
unsigned NumElts = VT.getVectorNumElements();

const TargetLowering &TLI = DAG.getTargetLoweringInfo();

if (TLI.getTypeAction(*DAG.getContext(), VT) !=
TargetLowering::TypeWidenVector)
return SDValue();

EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
unsigned WidenNumElts = WidenVT.getVectorNumElements();

SmallVector<SDValue, 16> NewOps(BV->op_begin(), BV->op_end());
assert(WidenNumElts >= NumElts && "Shrinking vector instead of widening!");
// Fill the new elements with Zero.
NewOps.append(WidenNumElts - NumElts, DAG.getConstant(0, dl, EltVT));
// Compute the step to place the elements in the right place and control the
// iteration.
unsigned step = WidenNumElts / NumElts;
if (WidenVT.is128BitVector()) {
if (step > 1 && Extend->getValueSizeInBits(0) == WidenVT.getSizeInBits()) {
for (int i = NumElts - 1, j = WidenNumElts - step; i > 0;
i--, j -= step) {
SDValue temp = NewOps[i];
NewOps[i] = NewOps[j];
NewOps[j] = temp;
}
// Create new build vector with WidenVT and NewOps
SDValue NewBV = DAG.getBuildVector(WidenVT, dl, NewOps);
// Replace the old build vector with the new one. Bitcast the
// new build vector to the type of the zext.
SDValue NewBVBitcast = DAG.getBitcast(ExtendVT, NewBV);
DAG.ReplaceAllUsesOfValueWith(SDValue(Extend, 0), NewBVBitcast);
return NewBV;
}
}
return SDValue();
}

SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
SDValue N0 = N->getOperand(0);
EVT VT = N->getValueType(0);
Expand Down Expand Up @@ -14621,6 +14686,9 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
return SDValue(CSENode, 0);
}

if (SDValue V = widenBuildVec(N, DAG))
return V;

return SDValue();
}

Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/PowerPC/custom-stov.ll
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Expand Up @@ -15,18 +15,18 @@ define void @_blah() {
; CHECK-NEXT: vperm v2, v4, v3, v2
; CHECK-NEXT: lwz r4, 16(0)
; CHECK-NEXT: stvx v2, 0, r5
; CHECK-NEXT: lhz r5, -64(r1)
; CHECK-NEXT: lhz r6, -58(r1)
; CHECK-NEXT: lhz r7, -52(r1)
; CHECK-NEXT: sth r4, -34(r1)
; CHECK-NEXT: sth r3, -36(r1)
; CHECK-NEXT: sth r3, -34(r1)
; CHECK-NEXT: sth r3, -38(r1)
; CHECK-NEXT: sth r3, -42(r1)
; CHECK-NEXT: sth r3, -46(r1)
; CHECK-NEXT: lhz r3, -52(r1)
; CHECK-NEXT: sth r3, -40(r1)
; CHECK-NEXT: lhz r3, -58(r1)
; CHECK-NEXT: sth r3, -44(r1)
; CHECK-NEXT: lhz r3, -64(r1)
; CHECK-NEXT: sth r4, -36(r1)
; CHECK-NEXT: sth r3, -48(r1)
; CHECK-NEXT: addi r3, r1, -48
; CHECK-NEXT: sth r7, -38(r1)
; CHECK-NEXT: sth r6, -42(r1)
; CHECK-NEXT: sth r5, -46(r1)
; CHECK-NEXT: lvx v2, 0, r3
; CHECK-NEXT: addi r3, r1, -32
; CHECK-NEXT: vsldoi v3, v2, v2, 8
Expand Down
30 changes: 24 additions & 6 deletions llvm/test/CodeGen/SystemZ/vec-mul-07.ll
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Expand Up @@ -7,7 +7,11 @@
define <8 x i16> @f1(<16 x i8> %val1, <16 x i8> %val2) {
; CHECK-LABEL: f1:
; CHECK: # %bb.0:
; CHECK-NEXT: vmleb %v24, %v24, %v26
; CHECK-NEXT: larl %r1, .LCPI0_0
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vperm %v1, %v24, %v0, %v0
; CHECK-NEXT: vperm %v0, %v26, %v0, %v0
; CHECK-NEXT: vmlhw %v24, %v1, %v0
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <16 x i8> %val1, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%zext1 = zext <8 x i8> %shuf1 to <8 x i16>
Expand All @@ -21,7 +25,12 @@ define <8 x i16> @f1(<16 x i8> %val1, <16 x i8> %val2) {
define <8 x i16> @f2(<16 x i8> %val1, <16 x i8> %val2) {
; CHECK-LABEL: f2:
; CHECK: # %bb.0:
; CHECK-NEXT: vmlob %v24, %v24, %v26
; CHECK-NEXT: larl %r1, .LCPI1_0
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vgbm %v1, 0
; CHECK-NEXT: vperm %v2, %v24, %v1, %v0
; CHECK-NEXT: vperm %v0, %v26, %v1, %v0
; CHECK-NEXT: vmlhw %v24, %v2, %v0
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <16 x i8> %val1, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%zext1 = zext <8 x i8> %shuf1 to <8 x i16>
Expand Down Expand Up @@ -63,7 +72,11 @@ define <8 x i16> @f4(<16 x i8> %val1, <16 x i8> %val2) {
define <4 x i32> @f5(<8 x i16> %val1, <8 x i16> %val2) {
; CHECK-LABEL: f5:
; CHECK: # %bb.0:
; CHECK-NEXT: vmleh %v24, %v24, %v26
; CHECK-NEXT: larl %r1, .LCPI4_0
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vperm %v1, %v24, %v0, %v0
; CHECK-NEXT: vperm %v0, %v26, %v0, %v0
; CHECK-NEXT: vmlf %v24, %v1, %v0
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <8 x i16> %val1, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%zext1 = zext <4 x i16> %shuf1 to <4 x i32>
Expand All @@ -77,7 +90,12 @@ define <4 x i32> @f5(<8 x i16> %val1, <8 x i16> %val2) {
define <4 x i32> @f6(<8 x i16> %val1, <8 x i16> %val2) {
; CHECK-LABEL: f6:
; CHECK: # %bb.0:
; CHECK-NEXT: vmloh %v24, %v24, %v26
; CHECK-NEXT: larl %r1, .LCPI5_0
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vgbm %v1, 0
; CHECK-NEXT: vperm %v2, %v24, %v1, %v0
; CHECK-NEXT: vperm %v0, %v26, %v1, %v0
; CHECK-NEXT: vmlf %v24, %v2, %v0
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <8 x i16> %val1, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%zext1 = zext <4 x i16> %shuf1 to <4 x i32>
Expand Down Expand Up @@ -119,7 +137,7 @@ define <4 x i32> @f8(<8 x i16> %val1, <8 x i16> %val2) {
define <2 x i64> @f9(<4 x i32> %val1, <4 x i32> %val2) {
; CHECK-LABEL: f9:
; CHECK: # %bb.0:
; CHECK-NEXT: vmlef %v24, %v24, %v26
; CHECK-NEXT: vgbm %v24, 0
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <4 x i32> %val1, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
%zext1 = zext <2 x i32> %shuf1 to <2 x i64>
Expand All @@ -133,7 +151,7 @@ define <2 x i64> @f9(<4 x i32> %val1, <4 x i32> %val2) {
define <2 x i64> @f10(<4 x i32> %val1, <4 x i32> %val2) {
; CHECK-LABEL: f10:
; CHECK: # %bb.0:
; CHECK-NEXT: vmlof %v24, %v24, %v26
; CHECK-NEXT: vgbm %v24, 0
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <4 x i32> %val1, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
%zext1 = zext <2 x i32> %shuf1 to <2 x i64>
Expand Down
30 changes: 24 additions & 6 deletions llvm/test/CodeGen/SystemZ/vec-mul-09.ll
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Expand Up @@ -7,7 +7,11 @@
define <8 x i16> @f1(<16 x i8> %val1, <16 x i8> %val2, <8 x i16> %val3) {
; CHECK-LABEL: f1:
; CHECK: # %bb.0:
; CHECK-NEXT: vmaleb %v24, %v24, %v26, %v28
; CHECK-NEXT: larl %r1, .LCPI0_0
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vperm %v1, %v24, %v0, %v0
; CHECK-NEXT: vperm %v0, %v26, %v0, %v0
; CHECK-NEXT: vmalhw %v24, %v1, %v0, %v28
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <16 x i8> %val1, <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%zext1 = zext <8 x i8> %shuf1 to <8 x i16>
Expand All @@ -22,7 +26,12 @@ define <8 x i16> @f1(<16 x i8> %val1, <16 x i8> %val2, <8 x i16> %val3) {
define <8 x i16> @f2(<16 x i8> %val1, <16 x i8> %val2, <8 x i16> %val3) {
; CHECK-LABEL: f2:
; CHECK: # %bb.0:
; CHECK-NEXT: vmalob %v24, %v24, %v26, %v28
; CHECK-NEXT: larl %r1, .LCPI1_0
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vgbm %v1, 0
; CHECK-NEXT: vperm %v2, %v24, %v1, %v0
; CHECK-NEXT: vperm %v0, %v26, %v1, %v0
; CHECK-NEXT: vmalhw %v24, %v2, %v0, %v28
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <16 x i8> %val1, <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%zext1 = zext <8 x i8> %shuf1 to <8 x i16>
Expand Down Expand Up @@ -67,7 +76,11 @@ define <8 x i16> @f4(<16 x i8> %val1, <16 x i8> %val2, <8 x i16> %val3) {
define <4 x i32> @f5(<8 x i16> %val1, <8 x i16> %val2, <4 x i32> %val3) {
; CHECK-LABEL: f5:
; CHECK: # %bb.0:
; CHECK-NEXT: vmaleh %v24, %v24, %v26, %v28
; CHECK-NEXT: larl %r1, .LCPI4_0
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vperm %v1, %v24, %v0, %v0
; CHECK-NEXT: vperm %v0, %v26, %v0, %v0
; CHECK-NEXT: vmalf %v24, %v1, %v0, %v28
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <8 x i16> %val1, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%zext1 = zext <4 x i16> %shuf1 to <4 x i32>
Expand All @@ -82,7 +95,12 @@ define <4 x i32> @f5(<8 x i16> %val1, <8 x i16> %val2, <4 x i32> %val3) {
define <4 x i32> @f6(<8 x i16> %val1, <8 x i16> %val2, <4 x i32> %val3) {
; CHECK-LABEL: f6:
; CHECK: # %bb.0:
; CHECK-NEXT: vmaloh %v24, %v24, %v26, %v28
; CHECK-NEXT: larl %r1, .LCPI5_0
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vgbm %v1, 0
; CHECK-NEXT: vperm %v2, %v24, %v1, %v0
; CHECK-NEXT: vperm %v0, %v26, %v1, %v0
; CHECK-NEXT: vmalf %v24, %v2, %v0, %v28
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <8 x i16> %val1, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%zext1 = zext <4 x i16> %shuf1 to <4 x i32>
Expand Down Expand Up @@ -127,7 +145,7 @@ define <4 x i32> @f8(<8 x i16> %val1, <8 x i16> %val2, <4 x i32> %val3) {
define <2 x i64> @f9(<4 x i32> %val1, <4 x i32> %val2, <2 x i64> %val3) {
; CHECK-LABEL: f9:
; CHECK: # %bb.0:
; CHECK-NEXT: vmalef %v24, %v24, %v26, %v28
; CHECK-NEXT: vlr %v24, %v28
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <4 x i32> %val1, <4 x i32> poison, <2 x i32> <i32 0, i32 2>
%zext1 = zext <2 x i32> %shuf1 to <2 x i64>
Expand All @@ -142,7 +160,7 @@ define <2 x i64> @f9(<4 x i32> %val1, <4 x i32> %val2, <2 x i64> %val3) {
define <2 x i64> @f10(<4 x i32> %val1, <4 x i32> %val2, <2 x i64> %val3) {
; CHECK-LABEL: f10:
; CHECK: # %bb.0:
; CHECK-NEXT: vmalof %v24, %v24, %v26, %v28
; CHECK-NEXT: vlr %v24, %v28
; CHECK-NEXT: br %r14
%shuf1 = shufflevector <4 x i32> %val1, <4 x i32> poison, <2 x i32> <i32 1, i32 3>
%zext1 = zext <2 x i32> %shuf1 to <2 x i64>
Expand Down
63 changes: 33 additions & 30 deletions llvm/test/CodeGen/WebAssembly/interleave.ll
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Expand Up @@ -17,13 +17,12 @@ define hidden void @accumulate8x2(ptr dead_on_unwind noalias writable sret(%stru
; CHECK-LABEL: accumulate8x2:
; CHECK: loop
; CHECK: v128.load64_zero
; CHECK: i8x16.shuffle 1, 3, 5, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
; CHECK: i16x8.extend_low_i8x16_u
; CHECK: i32x4.extend_low_i16x8_u
; CHECK: v128.const 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
; CHECK: local.tee 10
; CHECK: i8x16.shuffle 1, 17, 18, 19, 3, 21, 22, 23, 5, 25, 26, 27, 7, 29, 30, 31
; CHECK: i32x4.add
; CHECK: i8x16.shuffle 0, 2, 4, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
; CHECK: i16x8.extend_low_i8x16_u
; CHECK: i32x4.extend_low_i16x8_u
; CHECK: local.get 10
; CHECK: i8x16.shuffle 0, 17, 18, 19, 2, 21, 22, 23, 4, 25, 26, 27, 6, 29, 30, 31
; CHECK: i32x4.add
%4 = load i32, ptr %0, align 4
%5 = icmp eq i32 %2, 0
Expand Down Expand Up @@ -65,21 +64,18 @@ define hidden void @accumulate8x4(ptr dead_on_unwind noalias writable sret(%stru
; CHECK-LABEL: accumulate8x4
; CHECK: loop
; CHECK: v128.load
; CHECK: i8x16.shuffle 3, 7, 11, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
; CHECK: i16x8.extend_low_i8x16_u
; CHECK: i32x4.extend_low_i16x8_u
; CHECK: v128.const 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
; CHECK: local.tee 14
; CHECK: i8x16.shuffle 3, 17, 18, 19, 7, 21, 22, 23, 11, 25, 26, 27, 15, 29, 30, 31
; CHECK: i32x4.add
; CHECK: i8x16.shuffle 2, 6, 10, 14, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
; CHECK: i16x8.extend_low_i8x16_u
; CHECK: i32x4.extend_low_i16x8_u
; CHECK: local.get 14
; CHECK: i8x16.shuffle 2, 17, 18, 19, 6, 21, 22, 23, 10, 25, 26, 27, 14, 29, 30, 31
; CHECK: i32x4.add
; CHECK: i8x16.shuffle 1, 5, 9, 13, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
; CHECK: i16x8.extend_low_i8x16_u
; CHECK: i32x4.extend_low_i16x8_u
; CHECK: local.get 14
; CHECK: i8x16.shuffle 1, 17, 18, 19, 5, 21, 22, 23, 9, 25, 26, 27, 13, 29, 30, 31
; CHECK: i32x4.add
; CHECK: i8x16.shuffle 0, 4, 8, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
; CHECK: i16x8.extend_low_i8x16_u
; CHECK: i32x4.extend_low_i16x8_u
; CHECK: local.get 14
; CHECK: i8x16.shuffle 0, 17, 18, 19, 4, 21, 22, 23, 8, 25, 26, 27, 12, 29, 30, 31
; CHECK: i32x4.add
%4 = load i32, ptr %0, align 4
%5 = icmp eq i32 %2, 0
Expand Down Expand Up @@ -137,11 +133,12 @@ define hidden void @accumulate16x2(ptr dead_on_unwind noalias writable sret(%str
; CHECK-LABEL: accumulate16x2
; CHECK: loop
; CHECK: v128.load
; CHECK: i8x16.shuffle 2, 3, 6, 7, 10, 11, 14, 15, 0, 1, 0, 1, 0, 1, 0, 1
; CHECK: i32x4.extend_low_i16x8_u
; CHECK: v128.const 0, 0, 0, 0, 0, 0, 0, 0
; CHECK: local.tee 10
; CHECK: i8x16.shuffle 2, 3, 18, 19, 6, 7, 22, 23, 10, 11, 26, 27, 14, 15, 30, 31
; CHECK: i32x4.add
; CHECK: i8x16.shuffle 0, 1, 4, 5, 8, 9, 12, 13, 0, 1, 0, 1, 0, 1, 0, 1
; CHECK: i32x4.extend_low_i16x8_u
; CHECK: local.get 10
; CHECK: i8x16.shuffle 0, 1, 18, 19, 4, 5, 22, 23, 8, 9, 26, 27, 12, 13, 30, 31
; CHECK: i32x4.add
%4 = load i32, ptr %0, align 4
%5 = icmp eq i32 %2, 0
Expand Down Expand Up @@ -184,17 +181,23 @@ define hidden void @accumulate16x4(ptr dead_on_unwind noalias writable sret(%str
; CHECK: loop
; CHECK: v128.load 0:p2align=1
; CHECK: v128.load 16:p2align=1
; CHECK: i8x16.shuffle 6, 7, 14, 15, 22, 23, 30, 31, 0, 1, 0, 1, 0, 1, 0, 1
; CHECK: i32x4.extend_low_i16x8_u
; CHECK: i8x16.shuffle 6, 7, 0, 1, 14, 15, 0, 1, 22, 23, 0, 1, 30, 31, 0, 1
; CHECK: v128.const 0, 0, 0, 0, 0, 0, 0, 0
; CHECK: local.tee 15
; CHECK: i8x16.shuffle 0, 1, 18, 19, 4, 5, 22, 23, 8, 9, 26, 27, 12, 13, 30, 31

; CHECK: i32x4.add
; CHECK: i8x16.shuffle 4, 5, 12, 13, 20, 21, 28, 29, 0, 1, 0, 1, 0, 1, 0, 1
; CHECK: i32x4.extend_low_i16x8_u
; CHECK: i8x16.shuffle 4, 5, 0, 1, 12, 13, 0, 1, 20, 21, 0, 1, 28, 29, 0, 1
; CHECK: local.get 15
; CHECK: i8x16.shuffle 0, 1, 18, 19, 4, 5, 22, 23, 8, 9, 26, 27, 12, 13, 30, 31
; CHECK: i32x4.add
; CHECK: i8x16.shuffle 2, 3, 10, 11, 18, 19, 26, 27, 0, 1, 0, 1, 0, 1, 0, 1
; CHECK: i32x4.extend_low_i16x8_u
; CHECK: i8x16.shuffle 2, 3, 0, 1, 10, 11, 0, 1, 18, 19, 0, 1, 26, 27, 0, 1
; CHECK: local.get 15
; CHECK: i8x16.shuffle 0, 1, 18, 19, 4, 5, 22, 23, 8, 9, 26, 27, 12, 13, 30, 31
; CHECK: i32x4.add
; CHECK: i8x16.shuffle 0, 1, 8, 9, 16, 17, 24, 25, 0, 1, 0, 1, 0, 1, 0, 1
; CHECK: i32x4.extend_low_i16x8_u
; CHECK: i8x16.shuffle 0, 1, 0, 1, 8, 9, 0, 1, 16, 17, 0, 1, 24, 25, 0, 1
; CHECK: local.get 15
; CHECK: i8x16.shuffle 0, 1, 18, 19, 4, 5, 22, 23, 8, 9, 26, 27, 12, 13, 30, 31
; CHECK: i32x4.add
%4 = load i32, ptr %0, align 4
%5 = icmp eq i32 %2, 0
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