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[PowerPC] frontend get target feature from backend with cpu name #137670

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97f10e6
implement getting target features from backend for clang frontend
diggerlin Apr 25, 2025
23de679
clang format
diggerlin Apr 29, 2025
401cd0a
nit: code format
diggerlin Apr 30, 2025
e10686b
nit:clang format
diggerlin May 2, 2025
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148 changes: 7 additions & 141 deletions clang/lib/Basic/Targets/PPC.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,7 @@
#include "clang/Basic/MacroBuilder.h"
#include "clang/Basic/TargetBuiltins.h"
#include "llvm/TargetParser/PPCTargetParser.h"
#include <optional>

using namespace clang;
using namespace clang::targets;
Expand Down Expand Up @@ -516,129 +517,14 @@ static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags,
bool PPCTargetInfo::initFeatureMap(
llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
const std::vector<std::string> &FeaturesVec) const {
Features["altivec"] = llvm::StringSwitch<bool>(CPU)
.Case("7400", true)
.Case("g4", true)
.Case("7450", true)
.Case("g4+", true)
.Case("970", true)
.Case("g5", true)
.Case("pwr6", true)
.Case("pwr7", true)
.Case("pwr8", true)
.Case("pwr9", true)
.Case("ppc64", true)
.Case("ppc64le", true)
.Default(false);

Features["power9-vector"] = (CPU == "pwr9");
Features["crypto"] = llvm::StringSwitch<bool>(CPU)
.Case("ppc64le", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Default(false);
Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
.Case("ppc64le", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Default(false);
Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
.Case("ppc64le", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Case("pwr7", true)
.Default(false);
Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
.Case("ppc64le", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Case("pwr7", true)
.Default(false);
Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
.Case("ppc64le", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Default(false);
Features["crbits"] = llvm::StringSwitch<bool>(CPU)
.Case("ppc64le", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Default(false);
Features["vsx"] = llvm::StringSwitch<bool>(CPU)
.Case("ppc64le", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Case("pwr7", true)
.Default(false);
Features["htm"] = llvm::StringSwitch<bool>(CPU)
.Case("ppc64le", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Default(false);

// ROP Protect is off by default.
Features["rop-protect"] = false;
// Privileged instructions are off by default.
Features["privileged"] = false;

if (getTriple().isOSAIX()) {
// The code generated by the -maix-small-local-[exec|dynamic]-tls option is
// turned off by default.
Features["aix-small-local-exec-tls"] = false;
Features["aix-small-local-dynamic-tls"] = false;

// Turn off TLS model opt by default.
Features["aix-shared-lib-tls-model-opt"] = false;
}

Features["spe"] = llvm::StringSwitch<bool>(CPU)
.Case("8548", true)
.Case("e500", true)
.Default(false);

Features["isa-v206-instructions"] = llvm::StringSwitch<bool>(CPU)
.Case("ppc64le", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Case("pwr7", true)
.Case("a2", true)
.Default(false);

Features["isa-v207-instructions"] = llvm::StringSwitch<bool>(CPU)
.Case("ppc64le", true)
.Case("pwr9", true)
.Case("pwr8", true)
.Default(false);

Features["isa-v30-instructions"] =
llvm::StringSwitch<bool>(CPU).Case("pwr9", true).Default(false);

Features["quadword-atomics"] =
getTriple().isArch64Bit() && llvm::StringSwitch<bool>(CPU)
.Case("pwr9", true)
.Case("pwr8", true)
.Default(false);

// Power10 includes all the same features as Power9 plus any features specific
// to the Power10 core.
if (CPU == "pwr10" || CPU == "power10") {
initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
addP10SpecificFeatures(Features);
}

// Power11 includes all the same features as Power10 plus any features
// specific to the Power11 core.
if (CPU == "pwr11" || CPU == "power11") {
initFeatureMap(Features, Diags, "pwr10", FeaturesVec);
addP11SpecificFeatures(Features);
}
const llvm::Triple &TheTriple = getTriple();

// Future CPU should include all of the features of Power 11 as well as any
// additional features (yet to be determined) specific to it.
if (CPU == "future") {
initFeatureMap(Features, Diags, "pwr11", FeaturesVec);
addFutureSpecificFeatures(Features);
}
std::optional<llvm::StringMap<bool>> FeaturesOpt =
llvm::PPC::getPPCDefaultTargetFeatures(TheTriple,
llvm::PPC::normalizeCPUName(CPU));
if (FeaturesOpt.has_value())
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for optional, it's more popular to just use if (xxx) and *xxx

Features = FeaturesOpt.value();

if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
return false;
Expand Down Expand Up @@ -694,26 +580,6 @@ bool PPCTargetInfo::initFeatureMap(
return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
}

// Add any Power10 specific features.
void PPCTargetInfo::addP10SpecificFeatures(
llvm::StringMap<bool> &Features) const {
Features["htm"] = false; // HTM was removed for P10.
Features["paired-vector-memops"] = true;
Features["mma"] = true;
Features["power10-vector"] = true;
Features["pcrelative-memops"] = true;
Features["prefix-instrs"] = true;
Features["isa-v31-instructions"] = true;
}

// Add any Power11 specific features.
void PPCTargetInfo::addP11SpecificFeatures(
llvm::StringMap<bool> &Features) const {}

// Add features specific to the "Future" CPU.
void PPCTargetInfo::addFutureSpecificFeatures(
llvm::StringMap<bool> &Features) const {}

bool PPCTargetInfo::hasFeature(StringRef Feature) const {
return llvm::StringSwitch<bool>(Feature)
.Case("powerpc", true)
Expand Down
2 changes: 1 addition & 1 deletion clang/test/CodeGenCXX/cxx11-thread-local-reference.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -35,5 +35,5 @@ int &g() { return r; }
// DARWIN-LABEL: define internal cxx_fast_tlscc void @__tls_init()
// CHECK: call void @[[R_INIT]]()

// LINUX_AIX: attributes [[ATTR0]] = { {{.*}}"target-features"{{.*}} }
// LINUX_AIX: attributes [[ATTR0]] = { {{.*}} }
// DARWIN: attributes [[ATTR1]] = { {{.*}}nounwind{{.*}}"target-features"{{.*}} }
7 changes: 3 additions & 4 deletions clang/test/Driver/aix-shared-lib-tls-model-opt.c
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
// RUN: %clang -target powerpc64-unknown-aix -S -emit-llvm %s -o - | FileCheck --check-prefixes=CHECK-AIX,CHECK-AIX-OFF %s
// RUN: %clang -target powerpc-unknown-aix -S -emit-llvm %s -o - | FileCheck --check-prefixes=CHECK-AIX,CHECK-AIX-OFF %s
// RUN: %clang -target powerpc64-unknown-aix -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-AIX %s
// RUN: %clang -target powerpc-unknown-aix -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-AIX %s
// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-LINUX %s
// RUN: %clang -target powerpc64-unknown-linux-gnu -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-LINUX %s

Expand All @@ -19,9 +19,8 @@ int test(void) {

// CHECK-AIX: test() #0 {
// CHECK-AIX: attributes #0 = {
// CHECK-AIX-OFF-SAME: -aix-shared-lib-tls-model-opt
// CHECK-AIX-ON-SAME: +aix-shared-lib-tls-model-opt

// CHECK-LINUX-NOT: {{[-+]aix-shared-lib-tls-model-opt}}
// CHECK-LINUX-NOT: {{[+]aix-shared-lib-tls-model-opt}}

// CHECK-UNSUPPORTED-TARGET: option '-maix-shared-lib-tls-model-opt' cannot be specified on this target
15 changes: 7 additions & 8 deletions clang/test/Driver/aix-small-local-exec-dynamic-tls.c
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@@ -1,7 +1,7 @@
// RUN: %clang -target powerpc64-unknown-aix -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-AIX-DEFAULT %s
// RUN: %clang -target powerpc-unknown-aix -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-AIX-DEFAULT %s
// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-LINUX %s
// RUN: %clang -target powerpc64-unknown-linux-gnu -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-LINUX %s
// RUN: %clang -target powerpc64-unknown-aix -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-DEFAULT %s
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If you are updating RUN lines with %clang, replace long deprecated -target with --target=

// RUN: %clang -target powerpc-unknown-aix -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-DEFAULT %s
// RUN: %clang -target powerpc64le-unknown-linux-gnu -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-DEFAULT %s
// RUN: %clang -target powerpc64-unknown-linux-gnu -S -emit-llvm %s -o - | FileCheck --check-prefix=CHECK-DEFAULT %s

// RUN: %clang -target powerpc64-unknown-aix -maix-small-local-exec-tls -S -emit-llvm \
// RUN: %s -o - | FileCheck %s --check-prefix=CHECK-AIX_SMALL_LOCALEXEC_TLS
Expand Down Expand Up @@ -39,10 +39,9 @@ int test(void) {
return 0;
}

// CHECK-AIX-DEFAULT: test() #0 {
// CHECK-AIX-DEFAULT: attributes #0 = {
// CHECK-AIX-DEFAULT-SAME: {{-aix-small-local-exec-tls,.*-aix-small-local-dynamic-tls|-aix-small-local-dynamic-tls,.*-aix-small-local-exec-tls}}
// CHECK-LINUX-NOT: {{[-+]aix-small-local-exec-tls,.*[-+]aix-small-local-dynamic-tls|[-+]aix-small-local-dynamic-tls,.*[-+]aix-small-local-exec-tls}}
// CHECK-DEFAULT: test() #0 {
// CHECK-DEFAULT: attributes #0 = {
// CHECK-DEFAULT-NOT: {{[-+]aix-small-local-exec-tls,.*[-+]aix-small-local-dynamic-tls|[-+]aix-small-local-dynamic-tls,.*[-+]aix-small-local-exec-tls}}

// CHECK-UNSUPPORTED-AIX32: option '-maix-small-local-[exec|dynamic]-tls' cannot be specified on this target
// CHECK-UNSUPPORTED-LINUX: option '-maix-small-local-[exec|dynamic]-tls' cannot be specified on this target
Expand Down
4 changes: 0 additions & 4 deletions clang/test/Driver/ppc-crbits.cpp
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Expand Up @@ -64,8 +64,6 @@
// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mno-crbits \
// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS

// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -emit-llvm \
// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -mcrbits \
// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
// RUN: %clang -target powerpc64le-unknown-linux-gnu -mcpu=pwr7 -mno-crbits \
Expand All @@ -92,8 +90,6 @@
// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr8 -mno-crbits \
// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS

// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr7 -emit-llvm \
// RUN: -S %s -o - | FileCheck %s --check-prefix=HAS-NOCRBITS
// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr7 -mcrbits \
// RUN: -emit-llvm -S %s -o - | FileCheck %s --check-prefix=HAS-CRBITS
// RUN: %clang -target powerpc-ibm-aix -mcpu=pwr7 -mno-crbits \
Expand Down
22 changes: 11 additions & 11 deletions clang/test/Driver/ppc-isa-features.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5,20 +5,20 @@
// RUN: %clang -target powerpc64-unknown-aix -mcpu=pwr9 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-PWR9
// RUN: %clang -target powerpc-unknown-aix -mcpu=pwr10 -S -emit-llvm %s -o - | FileCheck %s -check-prefix=CHECK-PWR10

// CHECK-PWR6: -isa-v206-instructions
// CHECK-PWR6: -isa-v207-instructions
// CHECK-PWR6: -isa-v30-instructions
// CHECK-PWR6-NOT: isa-v206-instructions
// CHECK-PWR6-NOT: isa-v207-instructions
// CHECK-PWR6-NOT: isa-v30-instructions

// CHECK-A2: +isa-v206-instructions
// CHECK-A2: -isa-v207-instructions
// CHECK-A2: -isa-v30-instructions
// CHECK-A2: +isa-v206-instructions
// CHECK-A2-NOT: isa-v207-instructions
// CHECK-A2-NOT: isa-v30-instructions

// CHECK-PWR7: +isa-v206-instructions
// CHECK-PWR7: -isa-v207-instructions
// CHECK-PWR7: -isa-v30-instructions
// CHECK-PWR7: +isa-v206-instructions
// CHECK-PWR7-NOT: isa-v207-instructions
// CHECK-PWR7-NOT: isa-v30-instructions

// CHECK-PWR8: +isa-v207-instructions
// CHECK-PWR8: -isa-v30-instructions
// CHECK-PWR8: +isa-v207-instructions
// CHECK-PWR8-NOT: isa-v30-instructions

// CHECK-PWR9: +isa-v207-instructions
// CHECK-PWR9: +isa-v30-instructions
Expand Down
36 changes: 27 additions & 9 deletions llvm/include/llvm/MC/MCSubtargetInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,7 @@

#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/MC/MCInstrItineraries.h"
#include "llvm/MC/MCSchedule.h"
Expand All @@ -32,9 +33,8 @@ class MCInst;
//===----------------------------------------------------------------------===//

/// Used to provide key value pairs for feature and CPU bit flags.
struct SubtargetFeatureKV {
struct BasicSubtargetFeatureKV {
const char *Key; ///< K-V key string
const char *Desc; ///< Help descriptor
unsigned Value; ///< K-V integer value
FeatureBitArray Implies; ///< K-V bit mask

Expand All @@ -44,31 +44,49 @@ struct SubtargetFeatureKV {
}

/// Compare routine for std::is_sorted.
bool operator<(const SubtargetFeatureKV &Other) const {
bool operator<(const BasicSubtargetFeatureKV &Other) const {
return StringRef(Key) < StringRef(Other.Key);
}
BasicSubtargetFeatureKV(const char *Key, unsigned Value,
FeatureBitArray Implies)
: Key(Key), Value(Value), Implies(Implies) {}
};

struct SubtargetFeatureKV : BasicSubtargetFeatureKV {
const char *Desc; ///< Help descriptor
SubtargetFeatureKV(const char *Key, const char *Desc, unsigned Value,
FeatureBitArray Implies)
: BasicSubtargetFeatureKV(Key, Value, Implies), Desc(Desc) {}
};

//===----------------------------------------------------------------------===//

/// Used to provide key value pairs for feature and CPU bit flags.
struct SubtargetSubTypeKV {
const char *Key; ///< K-V key string
FeatureBitArray Implies; ///< K-V bit mask
FeatureBitArray TuneImplies; ///< K-V bit mask
const MCSchedModel *SchedModel;
struct BasicSubtargetSubTypeKV {
const char *Key; ///< K-V key string
FeatureBitArray Implies; ///< K-V bit mask

/// Compare routine for std::lower_bound
bool operator<(StringRef S) const {
return StringRef(Key) < S;
}

/// Compare routine for std::is_sorted.
bool operator<(const SubtargetSubTypeKV &Other) const {
bool operator<(const BasicSubtargetSubTypeKV &Other) const {
return StringRef(Key) < StringRef(Other.Key);
}
};

struct SubtargetSubTypeKV : BasicSubtargetSubTypeKV {
FeatureBitArray TuneImplies; ///< K-V bit mask
const MCSchedModel *SchedModel;
};

std::optional<llvm::StringMap<bool>>
getCPUDefaultTargetFeatures(StringRef CPU,
ArrayRef<BasicSubtargetSubTypeKV> ProcDesc,
ArrayRef<BasicSubtargetFeatureKV> ProcFeatures);

//===----------------------------------------------------------------------===//
///
/// Generic base class for all target subtargets.
Expand Down
5 changes: 5 additions & 0 deletions llvm/include/llvm/TargetParser/PPCTargetParser.h
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Expand Up @@ -14,7 +14,9 @@
#ifndef LLVM_TARGETPARSER_PPCTARGETPARSER_H
#define LLVM_TARGETPARSER_PPCTARGETPARSER_H

#include "llvm/ADT/StringMap.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/TargetParser/Triple.h"

namespace llvm {
Expand All @@ -34,6 +36,9 @@ StringRef getNormalizedPPCTuneCPU(const Triple &T, StringRef CPUName = "");
// For PPC, there are some cpu names for same CPU, like pwr10 and power10,
// normalize them.
StringRef normalizeCPUName(StringRef CPUName);

std::optional<llvm::StringMap<bool>>
getPPCDefaultTargetFeatures(const Triple &T, StringRef CPUName);
} // namespace PPC
} // namespace llvm

Expand Down
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