Skip to content

[SelectionDAG] Convert to or mask if all insertions are -1 #138213

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
wants to merge 1 commit into
base: main
Choose a base branch
from
+64 −255
Open

[SelectionDAG] Convert to or mask if all insertions are -1 #138213

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
21 changes: 16 additions & 5 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -22973,17 +22973,28 @@ SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) {
return NewShuffle;
}

// If all insertions are zero value, try to convert to AND mask.
// TODO: Do this for -1 with OR mask?
if (!LegalOperations && llvm::isNullConstant(InVal) &&
// We can convert to AND/OR mask if all insertions are zero or -1
// respectively.
if (!LegalOperations &&
(llvm::isNullConstant(InVal) || llvm::isAllOnesConstant(InVal)) &&
all_of(Ops, [InVal](SDValue Op) { return !Op || Op == InVal; }) &&
count_if(Ops, [InVal](SDValue Op) { return Op == InVal; }) >= 2) {
SDValue Zero = DAG.getConstant(0, DL, MaxEltVT);
SDValue AllOnes = DAG.getAllOnesConstant(DL, MaxEltVT);
SmallVector<SDValue, 8> Mask(NumElts);

// If all insertions are zero value, convert to AND mask.
if (llvm::isNullConstant(InVal)) {
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

You can share the loop for both cases by conditionally doing a std::swap of Zero/AllOnes and selecting the opcode.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Eh, do I want to do that?

Looks more confusing.

Copy link
Collaborator

@topperc topperc May 2, 2025 •
edited
Loading

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Then put the loop in a lambda and pass opcode, AllOnes, and AllZeros as arguments?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I would but this is a tiny one-line loop. It really is not worth the complexity.

Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I meant the getNode and getBuildVector too.

for (unsigned I = 0; I != NumElts; ++I)
Mask[I] = Ops[I] ? Zero : AllOnes;
return DAG.getNode(ISD::AND, DL, VT, CurVec,
DAG.getBuildVector(VT, DL, Mask));
}

// If all insertions are -1, convert to OR mask.
for (unsigned I = 0; I != NumElts; ++I)
Mask[I] = Ops[I] ? Zero : AllOnes;
return DAG.getNode(ISD::AND, DL, VT, CurVec,
Mask[I] = Ops[I] ? AllOnes : Zero;
return DAG.getNode(ISD::OR, DL, VT, CurVec,
DAG.getBuildVector(VT, DL, Mask));
}

Expand Down
16 changes: 5 additions & 11 deletions llvm/test/CodeGen/AArch64/vecreduce-and-legalization.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -101,19 +101,13 @@ define i8 @test_v3i8(<3 x i8> %a) nounwind {
define i8 @test_v9i8(<9 x i8> %a) nounwind {
; CHECK-LABEL: test_v9i8:
; CHECK: // %bb.0:
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: mov w8, #-1 // =0xffffffff
; CHECK-NEXT: mov v1.b[9], w8
; CHECK-NEXT: mov v1.b[10], w8
; CHECK-NEXT: mov v1.b[11], w8
; CHECK-NEXT: mov v1.b[12], w8
; CHECK-NEXT: mov v1.b[13], w8
; CHECK-NEXT: mov v1.b[14], w8
; CHECK-NEXT: mov v1.b[15], w8
; CHECK-NEXT: movi v1.2d, #0xffffff00ffffff00
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: orr v1.16b, v0.16b, v1.16b
; CHECK-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
; CHECK-NEXT: fmov x8, d0
; CHECK-NEXT: and x8, x8, x8, lsr #32
; CHECK-NEXT: fmov x9, d0
; CHECK-NEXT: and x8, x9, x8, lsr #32
; CHECK-NEXT: and x8, x8, x8, lsr #16
; CHECK-NEXT: lsr x9, x8, #8
; CHECK-NEXT: and w0, w8, w9
Expand Down
8 changes: 2 additions & 6 deletions llvm/test/CodeGen/X86/avx-cvt-3.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -48,17 +48,13 @@ define <8 x float> @sitofp_shuffle_zero_v8i32(<8 x i32> %a0) {
define <8 x float> @sitofp_insert_allbits_v8i32(<8 x i32> %a0) {
; X86-LABEL: sitofp_insert_allbits_v8i32:
; X86: # %bb.0:
; X86-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X86-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X86-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7]
; X86-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}, %ymm0, %ymm0
; X86-NEXT: vcvtdq2ps %ymm0, %ymm0
; X86-NEXT: retl
;
; X64-LABEL: sitofp_insert_allbits_v8i32:
; X64: # %bb.0:
; X64-NEXT: vxorps %xmm1, %xmm1, %xmm1
; X64-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1
; X64-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0],ymm0[1],ymm1[2],ymm0[3],ymm1[4,5],ymm0[6,7]
; X64-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
; X64-NEXT: vcvtdq2ps %ymm0, %ymm0
; X64-NEXT: retq
%1 = insertelement <8 x i32> %a0, i32 -1, i32 0
Expand Down
Loading